#include "target.h"
#include "target_type.h"
+#define __unused __attribute__((unused))
+
static const char * const armv8_state_strings[] = {
- "ARM", "Thumb", "Jazelle", "ThumbEE", "ARM64",
+ "AArch32", "Thumb", "Jazelle", "ThumbEE", "AArch64",
};
static const struct {
} armv8_mode_data[] = {
/* These special modes are currently only supported
* by ARMv6M and ARMv7M profiles */
+ {
+ .name = "USR",
+ .psr = ARM_MODE_USR,
+ },
+ {
+ .name = "FIQ",
+ .psr = ARM_MODE_FIQ,
+ },
+ {
+ .name = "IRQ",
+ .psr = ARM_MODE_IRQ,
+ },
+ {
+ .name = "SVC",
+ .psr = ARM_MODE_SVC,
+ },
+ {
+ .name = "MON",
+ .psr = ARM_MODE_MON,
+ },
+ {
+ .name = "ABT",
+ .psr = ARM_MODE_ABT,
+ },
{
.name = "EL0T",
.psr = ARMV8_64_EL0T,
}
}
+static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regval)
+{
+ struct arm_dpm *dpm = &armv8->dpm;
+ int retval;
+ uint32_t value;
+ uint64_t value_64;
+
+ switch (regnum) {
+ case 0 ... 30:
+ retval = dpm->instr_read_data_dcc_64(dpm,
+ ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, regnum), &value_64);
+ break;
+ case ARMV8_SP:
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MOVFSP_64(0), &value_64);
+ break;
+ case ARMV8_PC:
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS_DLR(0), &value_64);
+ break;
+ case ARMV8_xPSR:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS_DSPSR(0), &value);
+ value_64 = value;
+ break;
+ case ARMV8_ELR_EL1:
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_ELR_EL1, 0), &value_64);
+ break;
+ case ARMV8_ELR_EL2:
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_ELR_EL2, 0), &value_64);
+ break;
+ case ARMV8_ELR_EL3:
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_ELR_EL3, 0), &value_64);
+ break;
+ case ARMV8_ESR_EL1:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS(SYSTEM_ESR_EL1, 0), &value);
+ value_64 = value;
+ break;
+ case ARMV8_ESR_EL2:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS(SYSTEM_ESR_EL2, 0), &value);
+ value_64 = value;
+ break;
+ case ARMV8_ESR_EL3:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value);
+ value_64 = value;
+ break;
+ case ARMV8_SPSR_EL1:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS(SYSTEM_SPSR_EL1, 0), &value);
+ value_64 = value;
+ break;
+ case ARMV8_SPSR_EL2:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS(SYSTEM_SPSR_EL2, 0), &value);
+ value_64 = value;
+ break;
+ case ARMV8_SPSR_EL3:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS(SYSTEM_SPSR_EL3, 0), &value);
+ value_64 = value;
+ break;
+ default:
+ retval = ERROR_FAIL;
+ break;
+ }
+
+ if (retval == ERROR_OK && regval != NULL)
+ *regval = value_64;
+
+ return retval;
+}
-static int armv8_read_core_reg(struct target *target, struct reg *r,
- int num, enum arm_mode mode)
+static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t value_64)
{
- uint64_t reg_value;
+ struct arm_dpm *dpm = &armv8->dpm;
int retval;
- struct arm_reg *armv8_core_reg;
- struct armv8_common *armv8 = target_to_armv8(target);
+ uint32_t value;
- assert(num < (int)armv8->arm.core_cache->num_regs);
+ switch (regnum) {
+ case 0 ... 30:
+ retval = dpm->instr_write_data_dcc_64(dpm,
+ ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, regnum),
+ value_64);
+ break;
+ case ARMV8_SP:
+ retval = dpm->instr_write_data_r0_64(dpm,
+ ARMV8_MOVTSP_64(0),
+ value_64);
+ break;
+ case ARMV8_PC:
+ retval = dpm->instr_write_data_r0_64(dpm,
+ ARMV8_MSR_DLR(0),
+ value_64);
+ break;
+ case ARMV8_xPSR:
+ value = value_64;
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MSR_DSPSR(0),
+ value);
+ break;
+ /* registers clobbered by taking exception in debug state */
+ case ARMV8_ELR_EL1:
+ retval = dpm->instr_write_data_r0_64(dpm,
+ ARMV8_MSR_GP(SYSTEM_ELR_EL1, 0), value_64);
+ break;
+ case ARMV8_ELR_EL2:
+ retval = dpm->instr_write_data_r0_64(dpm,
+ ARMV8_MSR_GP(SYSTEM_ELR_EL2, 0), value_64);
+ break;
+ case ARMV8_ELR_EL3:
+ retval = dpm->instr_write_data_r0_64(dpm,
+ ARMV8_MSR_GP(SYSTEM_ELR_EL3, 0), value_64);
+ break;
+ case ARMV8_ESR_EL1:
+ value = value_64;
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MSR_GP(SYSTEM_ESR_EL1, 0), value);
+ break;
+ case ARMV8_ESR_EL2:
+ value = value_64;
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MSR_GP(SYSTEM_ESR_EL2, 0), value);
+ break;
+ case ARMV8_ESR_EL3:
+ value = value_64;
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value);
+ break;
+ case ARMV8_SPSR_EL1:
+ value = value_64;
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value);
+ break;
+ case ARMV8_SPSR_EL2:
+ value = value_64;
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MSR_GP(SYSTEM_SPSR_EL2, 0), value);
+ break;
+ case ARMV8_SPSR_EL3:
+ value = value_64;
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MSR_GP(SYSTEM_SPSR_EL3, 0), value);
+ break;
+ default:
+ retval = ERROR_FAIL;
+ break;
+ }
- armv8_core_reg = armv8->arm.core_cache->reg_list[num].arch_info;
- retval = armv8->load_core_reg_u64(target,
- armv8_core_reg->num, ®_value);
+ return retval;
+}
- buf_set_u64(armv8->arm.core_cache->reg_list[num].value, 0, 64, reg_value);
- armv8->arm.core_cache->reg_list[num].valid = 1;
- armv8->arm.core_cache->reg_list[num].dirty = 0;
+static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *regval)
+{
+ struct arm_dpm *dpm = &armv8->dpm;
+ uint32_t value = 0;
+ int retval;
+
+ switch (regnum) {
+ case ARMV8_R0 ... ARMV8_R14:
+ /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
+ retval = dpm->instr_read_data_dcc(dpm,
+ ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
+ &value);
+ break;
+ case ARMV8_SP:
+ retval = dpm->instr_read_data_dcc(dpm,
+ ARMV4_5_MCR(14, 0, 13, 0, 5, 0),
+ &value);
+ break;
+ case ARMV8_PC:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRC_DLR(0),
+ &value);
+ break;
+ case ARMV8_xPSR:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRC_DSPSR(0),
+ &value);
+ break;
+ case ARMV8_ELR_EL1: /* mapped to LR_svc */
+ retval = dpm->instr_read_data_dcc(dpm,
+ ARMV4_5_MCR(14, 0, 14, 0, 5, 0),
+ &value);
+ break;
+ case ARMV8_ELR_EL2: /* mapped to ELR_hyp */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS_T1(0, 14, 0, 1),
+ &value);
+ break;
+ case ARMV8_ELR_EL3: /* mapped to LR_mon */
+ retval = dpm->instr_read_data_dcc(dpm,
+ ARMV4_5_MCR(14, 0, 14, 0, 5, 0),
+ &value);
+ break;
+ case ARMV8_ESR_EL1: /* mapped to DFSR */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
+ &value);
+ break;
+ case ARMV8_ESR_EL2: /* mapped to HSR */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 4, 0, 5, 2, 0),
+ &value);
+ break;
+ case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */
+ retval = ERROR_FAIL;
+ break;
+ case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS_xPSR_T1(1, 0),
+ &value);
+ break;
+ case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS_xPSR_T1(1, 0),
+ &value);
+ break;
+ case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS_xPSR_T1(1, 0),
+ &value);
+ break;
+ default:
+ retval = ERROR_FAIL;
+ break;
+ }
+
+ if (retval == ERROR_OK && regval != NULL)
+ *regval = value;
return retval;
}
-#if 0
-static int armv8_write_core_reg(struct target *target, struct reg *r,
- int num, enum arm_mode mode, target_addr_t value)
+static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t value)
{
+ struct arm_dpm *dpm = &armv8->dpm;
int retval;
- struct arm_reg *armv8_core_reg;
- struct armv8_common *armv8 = target_to_armv8(target);
- assert(num < (int)armv8->arm.core_cache->num_regs);
+ switch (regnum) {
+ case ARMV8_R0 ... ARMV8_R14:
+ /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
+ retval = dpm->instr_write_data_dcc(dpm,
+ ARMV4_5_MRC(14, 0, regnum, 0, 5, 0), value);
+ break;
+ case ARMV8_SP:
+ retval = dpm->instr_write_data_dcc(dpm,
+ ARMV4_5_MRC(14, 0, 13, 0, 5, 0),
+ value);
+ break;
+ case ARMV8_PC:/* PC
+ * read r0 from DCC; then "MOV pc, r0" */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MCR_DLR(0), value);
+ break;
+ case ARMV8_xPSR: /* CPSR */
+ /* read r0 from DCC, then "MCR r0, DSPSR" */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MCR_DSPSR(0), value);
+ break;
+ case ARMV8_ELR_EL1: /* mapped to LR_svc */
+ retval = dpm->instr_write_data_dcc(dpm,
+ ARMV4_5_MRC(14, 0, 14, 0, 5, 0),
+ value);
+ break;
+ case ARMV8_ELR_EL2: /* mapped to ELR_hyp */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MSR_GP_T1(0, 14, 0, 1),
+ value);
+ break;
+ case ARMV8_ELR_EL3: /* mapped to LR_mon */
+ retval = dpm->instr_write_data_dcc(dpm,
+ ARMV4_5_MRC(14, 0, 14, 0, 5, 0),
+ value);
+ break;
+ case ARMV8_ESR_EL1: /* mapped to DFSR */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MCR(15, 0, 0, 5, 0, 0),
+ value);
+ break;
+ case ARMV8_ESR_EL2: /* mapped to HSR */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MCR(15, 4, 0, 5, 2, 0),
+ value);
+ break;
+ case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */
+ retval = ERROR_FAIL;
+ break;
+ case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+ value);
+ break;
+ case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+ value);
+ break;
+ case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+ value);
+ break;
+ default:
+ retval = ERROR_FAIL;
+ break;
+ }
+
+ return retval;
- armv8_core_reg = armv8->arm.core_cache->reg_list[num].arch_info;
- retval = armv8->store_core_reg_u64(target,
- armv8_core_reg->num,
- value);
- if (retval != ERROR_OK) {
- LOG_ERROR("JTAG failure");
- armv8->arm.core_cache->reg_list[num].dirty = armv8->arm.core_cache->reg_list[num].valid;
- return ERROR_JTAG_DEVICE_ERROR;
+}
+
+void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64)
+{
+ if (is_aarch64) {
+ armv8->read_reg_u64 = armv8_read_reg;
+ armv8->write_reg_u64 = armv8_write_reg;
+ } else {
+ armv8->read_reg_u64 = armv8_read_reg32;
+ armv8->write_reg_u64 = armv8_write_reg32;
}
+}
- LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, value);
- armv8->arm.core_cache->reg_list[num].valid = 1;
- armv8->arm.core_cache->reg_list[num].dirty = 0;
+/* retrieve core id cluster id */
+int armv8_read_mpidr(struct armv8_common *armv8)
+{
+ int retval = ERROR_FAIL;
+ struct arm_dpm *dpm = armv8->arm.dpm;
+ uint32_t mpidr;
- return ERROR_OK;
+ retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ goto done;
+
+ retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
+ if (retval != ERROR_OK)
+ goto done;
+ if (mpidr & 1<<31) {
+ armv8->multi_processor_system = (mpidr >> 30) & 1;
+ armv8->cluster_id = (mpidr >> 8) & 0xf;
+ armv8->cpu_id = mpidr & 0x3;
+ LOG_INFO("%s cluster %x core %x %s", target_name(armv8->arm.target),
+ armv8->cluster_id,
+ armv8->cpu_id,
+ armv8->multi_processor_system == 0 ? "multi core" : "mono core");
+
+ } else
+ LOG_ERROR("mpdir not in multiprocessor format");
+
+done:
+ dpm->finish(dpm);
+ return retval;
}
-#endif
+
/**
* Configures host-side ARM records to reflect the specified CPSR.
* Later, code can use arm_reg_current() to map register numbers
}
}
arm->core_state = state;
- if (arm->core_state == ARM_STATE_AARCH64) {
- switch (mode) {
- case SYSTEM_AAR64_MODE_EL0t:
- arm->core_mode = ARMV8_64_EL0T;
- break;
- case SYSTEM_AAR64_MODE_EL1t:
- arm->core_mode = ARMV8_64_EL0T;
- break;
- case SYSTEM_AAR64_MODE_EL1h:
- arm->core_mode = ARMV8_64_EL1H;
- break;
- case SYSTEM_AAR64_MODE_EL2t:
- arm->core_mode = ARMV8_64_EL2T;
- break;
- case SYSTEM_AAR64_MODE_EL2h:
- arm->core_mode = ARMV8_64_EL2H;
- break;
- case SYSTEM_AAR64_MODE_EL3t:
- arm->core_mode = ARMV8_64_EL3T;
- break;
- case SYSTEM_AAR64_MODE_EL3h:
- arm->core_mode = ARMV8_64_EL3H;
- break;
- default:
- LOG_DEBUG("unknow mode 0x%x", (unsigned) (mode));
- break;
- }
- } else {
+ if (arm->core_state == ARM_STATE_AARCH64)
+ arm->core_mode = (mode << 4) | 0xf;
+ else
arm->core_mode = mode;
- }
LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
armv8_mode_name(arm->core_mode),
armv8_state_strings[arm->core_state]);
}
+static void armv8_show_fault_registers32(struct armv8_common *armv8)
+{
+ uint32_t dfsr, ifsr, dfar, ifar;
+ struct arm_dpm *dpm = armv8->arm.dpm;
+ int retval;
+
+ retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ return;
+
+ /* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
+
+ /* c5/c0 - {data, instruction} fault status registers */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
+ &dfsr);
+ if (retval != ERROR_OK)
+ goto done;
+
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 5, 0, 1),
+ &ifsr);
+ if (retval != ERROR_OK)
+ goto done;
+
+ /* c6/c0 - {data, instruction} fault address registers */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 6, 0, 0),
+ &dfar);
+ if (retval != ERROR_OK)
+ goto done;
+
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 6, 0, 2),
+ &ifar);
+ if (retval != ERROR_OK)
+ goto done;
+
+ LOG_USER("Data fault registers DFSR: %8.8" PRIx32
+ ", DFAR: %8.8" PRIx32, dfsr, dfar);
+ LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
+ ", IFAR: %8.8" PRIx32, ifsr, ifar);
+
+done:
+ /* (void) */ dpm->finish(dpm);
+}
+
static void armv8_show_fault_registers(struct target *target)
{
- /* TODO */
+ struct armv8_common *armv8 = target_to_armv8(target);
+
+ if (armv8->arm.core_state != ARM_STATE_AARCH64)
+ armv8_show_fault_registers32(armv8);
}
static uint8_t armv8_pa_size(uint32_t ps)
return ret;
}
-static int armv8_read_ttbcr(struct target *target)
+static __unused int armv8_read_ttbcr32(struct target *target)
+{
+ struct armv8_common *armv8 = target_to_armv8(target);
+ struct arm_dpm *dpm = armv8->arm.dpm;
+ uint32_t ttbcr, ttbcr_n;
+ int retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ goto done;
+ /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
+ &ttbcr);
+ if (retval != ERROR_OK)
+ goto done;
+
+ LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
+
+ ttbcr_n = ttbcr & 0x7;
+ armv8->armv8_mmu.ttbcr = ttbcr;
+
+ /*
+ * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+ * document # ARM DDI 0406C
+ */
+ armv8->armv8_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n;
+ armv8->armv8_mmu.ttbr_range[1] = 0xffffffff;
+ armv8->armv8_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
+ armv8->armv8_mmu.ttbr_mask[1] = 0xffffffff << 14;
+
+ LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
+ (ttbcr_n != 0) ? "used" : "not used",
+ armv8->armv8_mmu.ttbr_mask[0],
+ armv8->armv8_mmu.ttbr_mask[1]);
+
+done:
+ dpm->finish(dpm);
+ return retval;
+}
+
+static __unused int armv8_read_ttbcr(struct target *target)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
- switch (arm->core_mode) {
- case ARMV8_64_EL3H:
- case ARMV8_64_EL3T:
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_TCR_EL3, 0),
- &ttbcr);
- retval += dpm->instr_read_data_r0_64(dpm,
- ARMV8_MRS(SYSTEM_TTBR0_EL3, 0),
- &armv8->ttbr_base);
- if (retval != ERROR_OK)
- goto done;
- armv8->va_size = 64 - (ttbcr & 0x3F);
- armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
- armv8->page_size = (ttbcr >> 14) & 3;
- break;
- case ARMV8_64_EL2T:
- case ARMV8_64_EL2H:
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_TCR_EL2, 0),
- &ttbcr);
- retval += dpm->instr_read_data_r0_64(dpm,
- ARMV8_MRS(SYSTEM_TTBR0_EL2, 0),
- &armv8->ttbr_base);
- if (retval != ERROR_OK)
- goto done;
- armv8->va_size = 64 - (ttbcr & 0x3F);
- armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
- armv8->page_size = (ttbcr >> 14) & 3;
- break;
- case ARMV8_64_EL0T:
- case ARMV8_64_EL1T:
- case ARMV8_64_EL1H:
- retval = dpm->instr_read_data_r0_64(dpm,
- ARMV8_MRS(SYSTEM_TCR_EL1, 0),
- &ttbcr_64);
- armv8->va_size = 64 - (ttbcr_64 & 0x3F);
- armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7);
- armv8->page_size = (ttbcr_64 >> 14) & 3;
- armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0;
- armv8->armv8_mmu.ttbr0_mask = 0x0000FFFFFFFFFFFF;
- retval += dpm->instr_read_data_r0_64(dpm,
- ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0),
- &armv8->ttbr_base);
- if (retval != ERROR_OK)
- goto done;
- break;
- default:
- LOG_ERROR("unknow core state");
- retval = ERROR_FAIL;
- break;
+ switch (armv8_curel_from_core_mode(arm->core_mode)) {
+ case SYSTEM_CUREL_EL3:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS(SYSTEM_TCR_EL3, 0),
+ &ttbcr);
+ retval += dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_TTBR0_EL3, 0),
+ &armv8->ttbr_base);
+ if (retval != ERROR_OK)
+ goto done;
+ armv8->va_size = 64 - (ttbcr & 0x3F);
+ armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
+ armv8->page_size = (ttbcr >> 14) & 3;
+ break;
+ case SYSTEM_CUREL_EL2:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS(SYSTEM_TCR_EL2, 0),
+ &ttbcr);
+ retval += dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_TTBR0_EL2, 0),
+ &armv8->ttbr_base);
+ if (retval != ERROR_OK)
+ goto done;
+ armv8->va_size = 64 - (ttbcr & 0x3F);
+ armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
+ armv8->page_size = (ttbcr >> 14) & 3;
+ break;
+ case SYSTEM_CUREL_EL0:
+ armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
+ /* fall through */
+ case SYSTEM_CUREL_EL1:
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_TCR_EL1, 0),
+ &ttbcr_64);
+ armv8->va_size = 64 - (ttbcr_64 & 0x3F);
+ armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7);
+ armv8->page_size = (ttbcr_64 >> 14) & 3;
+ armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0;
+ armv8->armv8_mmu.ttbr0_mask = 0x0000FFFFFFFFFFFF;
+ retval += dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0),
+ &armv8->ttbr_base);
+ if (retval != ERROR_OK)
+ goto done;
+ break;
+ default:
+ LOG_ERROR("unknow core state");
+ retval = ERROR_FAIL;
+ break;
}
if (retval != ERROR_OK)
goto done;
-#if 0
- LOG_INFO("ttb1 %s ,ttb0_mask %llx",
- armv8->armv8_mmu.ttbr1_used ? "used" : "not used",
- armv8->armv8_mmu.ttbr0_mask);
-#endif
- if (armv8->armv8_mmu.ttbr1_used == 1) {
- LOG_INFO("TTBR0 access above %" PRIx64,
- (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
- armv8->armv8_mmu.os_border = armv8->armv8_mmu.ttbr0_mask;
- } else {
- /* fix me , default is hard coded LINUX border */
- armv8->armv8_mmu.os_border = 0xc0000000;
- }
+ if (armv8->armv8_mmu.ttbr1_used == 1)
+ LOG_INFO("TTBR0 access above %" PRIx64, (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
+
done:
+ armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
dpm->finish(dpm);
return retval;
}
-static int armv8_4K_translate(struct target *target, uint32_t va, uint32_t *val)
+/* method adapted to cortex A : reused arm v4 v5 method*/
+int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val)
{
- LOG_ERROR("4K page Address translation need to add");
- return ERROR_FAIL;
+ return ERROR_OK;
}
-
-/* method adapted to cortex A : reused arm v4 v5 method*/
-int armv8_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
+/* V8 method VA TO PA */
+int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
+ target_addr_t *val, int meminfo)
{
- int retval = ERROR_FAIL;
struct armv8_common *armv8 = target_to_armv8(target);
- struct arm_dpm *dpm = armv8->arm.dpm;
+ struct arm *arm = target_to_arm(target);
+ struct arm_dpm *dpm = &armv8->dpm;
+ enum arm_mode target_mode = ARM_MODE_ANY;
+ uint32_t retval;
+ uint32_t instr = 0;
+ uint64_t par;
+
+ static const char * const shared_name[] = {
+ "Non-", "UNDEFINED ", "Outer ", "Inner "
+ };
+
+ static const char * const secure_name[] = {
+ "Secure", "Not Secure"
+ };
retval = dpm->prepare(dpm);
- retval += armv8_read_ttbcr(target);
if (retval != ERROR_OK)
- goto done;
- if (armv8->page_size == 0)
- return armv8_4K_translate(target, va, val);
+ return retval;
-done:
- dpm->finish(dpm);
- return ERROR_FAIL;
-}
+ switch (armv8_curel_from_core_mode(arm->core_mode)) {
+ case SYSTEM_CUREL_EL0:
+ instr = ARMV8_SYS(SYSTEM_ATS12E0R, 0);
+ /* can only execute instruction at EL2 */
+ target_mode = ARMV8_64_EL2H;
+ break;
+ case SYSTEM_CUREL_EL1:
+ instr = ARMV8_SYS(SYSTEM_ATS12E1R, 0);
+ /* can only execute instruction at EL2 */
+ target_mode = ARMV8_64_EL2H;
+ break;
+ case SYSTEM_CUREL_EL2:
+ instr = ARMV8_SYS(SYSTEM_ATS1E2R, 0);
+ break;
+ case SYSTEM_CUREL_EL3:
+ instr = ARMV8_SYS(SYSTEM_ATS1E3R, 0);
+ break;
-/* V8 method VA TO PA */
-int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
- target_addr_t *val, int meminfo)
-{
- return ERROR_OK;
-}
+ default:
+ break;
+ };
-static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx,
- struct armv8_cache_common *armv8_cache)
-{
- if (armv8_cache->ctype == -1) {
- command_print(cmd_ctx, "cache not yet identified");
- return ERROR_OK;
- }
+ if (target_mode != ARM_MODE_ANY)
+ armv8_dpm_modeswitch(dpm, target_mode);
- command_print(cmd_ctx,
- "D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
- armv8_cache->d_u_size.linelen,
- armv8_cache->d_u_size.associativity,
- armv8_cache->d_u_size.nsets,
- armv8_cache->d_u_size.cachesize);
+ /* write VA to R0 and execute translation instruction */
+ retval = dpm->instr_write_data_r0_64(dpm, instr, (uint64_t)va);
+ /* read result from PAR_EL1 */
+ if (retval == ERROR_OK)
+ retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_PAR_EL1, 0), &par);
- command_print(cmd_ctx,
- "I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
- armv8_cache->i_size.linelen,
- armv8_cache->i_size.associativity,
- armv8_cache->i_size.nsets,
- armv8_cache->i_size.cachesize);
+ /* switch back to saved PE mode */
+ if (target_mode != ARM_MODE_ANY)
+ armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
- return ERROR_OK;
-}
+ dpm->finish(dpm);
-static int _armv8_flush_all_data(struct target *target)
-{
- struct armv8_common *armv8 = target_to_armv8(target);
- struct arm_dpm *dpm = armv8->arm.dpm;
- struct armv8_cachesize *d_u_size =
- &(armv8->armv8_mmu.armv8_cache.d_u_size);
- int32_t c_way, c_index = d_u_size->index;
- int retval;
- /* check that cache data is on at target halt */
- if (!armv8->armv8_mmu.armv8_cache.d_u_cache_enabled) {
- LOG_INFO("flushed not performed :cache not on at target halt");
- return ERROR_OK;
- }
- retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
- goto done;
- do {
- c_way = d_u_size->way;
- do {
- uint32_t value = (c_index << d_u_size->index_shift)
- | (c_way << d_u_size->way_shift);
- /* DCCISW */
- /* LOG_INFO ("%d %d %x",c_way,c_index,value); */
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP(SYSTEM_DCCISW, 0),
- value);
- if (retval != ERROR_OK)
- goto done;
- c_way -= 1;
- } while (c_way >= 0);
- c_index -= 1;
- } while (c_index >= 0);
- return retval;
-done:
- LOG_ERROR("flushed failed");
- dpm->finish(dpm);
- return retval;
-}
+ return retval;
-static int armv8_flush_all_data(struct target *target)
-{
- int retval = ERROR_FAIL;
- /* check that armv8_cache is correctly identify */
- struct armv8_common *armv8 = target_to_armv8(target);
- if (armv8->armv8_mmu.armv8_cache.ctype == -1) {
- LOG_ERROR("trying to flush un-identified cache");
+ if (retval != ERROR_OK)
return retval;
- }
- if (target->smp) {
- /* look if all the other target have been flushed in order to flush level
- * 2 */
- struct target_list *head;
- struct target *curr;
- head = target->head;
- while (head != (struct target_list *)NULL) {
- curr = head->target;
- if (curr->state == TARGET_HALTED) {
- LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
- retval = _armv8_flush_all_data(curr);
- }
- head = head->next;
+ if (par & 1) {
+ LOG_ERROR("Address translation failed at stage %i, FST=%x, PTW=%i",
+ ((int)(par >> 9) & 1)+1, (int)(par >> 1) & 0x3f, (int)(par >> 8) & 1);
+
+ *val = 0;
+ retval = ERROR_FAIL;
+ } else {
+ *val = (par & 0xFFFFFFFFF000UL) | (va & 0xFFF);
+ if (meminfo) {
+ int SH = (par >> 7) & 3;
+ int NS = (par >> 9) & 1;
+ int ATTR = (par >> 56) & 0xFF;
+
+ char *memtype = (ATTR & 0xF0) == 0 ? "Device Memory" : "Normal Memory";
+
+ LOG_USER("%sshareable, %s",
+ shared_name[SH], secure_name[NS]);
+ LOG_USER("%s", memtype);
}
- } else
- retval = _armv8_flush_all_data(target);
+ }
+
return retval;
}
int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
struct armv8_cache_common *armv8_cache)
{
- if (armv8_cache->ctype == -1) {
+ if (armv8_cache->info == -1) {
command_print(cmd_ctx, "cache not yet identified");
return ERROR_OK;
}
return ERROR_OK;
}
-/* retrieve core id cluster id */
-static int armv8_read_mpidr(struct target *target)
-{
- int retval = ERROR_FAIL;
- struct armv8_common *armv8 = target_to_armv8(target);
- struct arm_dpm *dpm = armv8->arm.dpm;
- uint32_t mpidr;
- retval = dpm->prepare(dpm);
- if (retval != ERROR_OK)
- goto done;
- /* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/
-
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_MPIDR, 0),
- &mpidr);
- if (retval != ERROR_OK)
- goto done;
- if (mpidr & 1<<31) {
- armv8->multi_processor_system = (mpidr >> 30) & 1;
- armv8->cluster_id = (mpidr >> 8) & 0xf;
- armv8->cpu_id = mpidr & 0x3;
- LOG_INFO("%s cluster %x core %x %s", target_name(target),
- armv8->cluster_id,
- armv8->cpu_id,
- armv8->multi_processor_system == 0 ? "multi core" : "mono core");
-
- } else
- LOG_ERROR("mpdir not in multiprocessor format");
-
-done:
- dpm->finish(dpm);
- return retval;
-
-
-}
-
-int armv8_identify_cache(struct target *target)
-{
- /* read cache descriptor */
- int retval = ERROR_FAIL;
- struct armv8_common *armv8 = target_to_armv8(target);
- struct arm_dpm *dpm = armv8->arm.dpm;
- uint32_t cache_selected, clidr;
- uint32_t cache_i_reg, cache_d_reg;
- struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
- armv8_read_ttbcr(target);
- retval = dpm->prepare(dpm);
-
- if (retval != ERROR_OK)
- goto done;
- /* retrieve CLIDR
- * mrc p15, 1, r0, c0, c0, 1 @ read clidr */
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CLIDR, 0),
- &clidr);
- if (retval != ERROR_OK)
- goto done;
- clidr = (clidr & 0x7000000) >> 23;
- LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
- if ((clidr / 2) > 1) {
- /* FIXME not supported present in cortex A8 and later */
- /* in cortex A7, A15 */
- LOG_ERROR("cache l2 present :not supported");
- }
- /* retrieve selected cache*/
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CSSELR, 0),
- &cache_selected);
- if (retval != ERROR_OK)
- goto done;
-
-
- /* select instruction cache
- * [0] : 1 instruction cache selection , 0 data cache selection */
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CSSELR, 0),
- 1);
- if (retval != ERROR_OK)
- goto done;
-
- /* read CCSIDR
- * MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
- * [2:0] line size 001 eight word per line
- * [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CCSIDR, 0),
- &cache_i_reg);
- if (retval != ERROR_OK)
- goto done;
-
- /* select data cache*/
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CSSELR, 0),
- 0);
- if (retval != ERROR_OK)
- goto done;
-
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CCSIDR, 0),
- &cache_d_reg);
- if (retval != ERROR_OK)
- goto done;
-
- /* restore selected cache */
- dpm->instr_write_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CSSELR, 0),
- cache_selected);
-
- if (retval != ERROR_OK)
- goto done;
- dpm->finish(dpm);
-
- /* put fake type */
- cache->d_u_size.linelen = 16 << (cache_d_reg & 0x7);
- cache->d_u_size.cachesize = (((cache_d_reg >> 13) & 0x7fff)+1)/8;
- cache->d_u_size.nsets = (cache_d_reg >> 13) & 0x7fff;
- cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) + 1;
- /* compute info for set way operation on cache */
- cache->d_u_size.index_shift = (cache_d_reg & 0x7) + 4;
- cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff;
- cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff);
- cache->d_u_size.way_shift = cache->d_u_size.way + 1;
- {
- int i = 0;
- while (((cache->d_u_size.way_shift >> i) & 1) != 1)
- i++;
- cache->d_u_size.way_shift = 32-i;
- }
-#if 0
- LOG_INFO("data cache index %d << %d, way %d << %d",
- cache->d_u_size.index, cache->d_u_size.index_shift,
- cache->d_u_size.way,
- cache->d_u_size.way_shift);
-
- LOG_INFO("data cache %d bytes %d KBytes asso %d ways",
- cache->d_u_size.linelen,
- cache->d_u_size.cachesize,
- cache->d_u_size.associativity);
-#endif
- cache->i_size.linelen = 16 << (cache_i_reg & 0x7);
- cache->i_size.associativity = ((cache_i_reg >> 3) & 0x3ff) + 1;
- cache->i_size.nsets = (cache_i_reg >> 13) & 0x7fff;
- cache->i_size.cachesize = (((cache_i_reg >> 13) & 0x7fff)+1)/8;
- /* compute info for set way operation on cache */
- cache->i_size.index_shift = (cache_i_reg & 0x7) + 4;
- cache->i_size.index = (cache_i_reg >> 13) & 0x7fff;
- cache->i_size.way = ((cache_i_reg >> 3) & 0x3ff);
- cache->i_size.way_shift = cache->i_size.way + 1;
- {
- int i = 0;
- while (((cache->i_size.way_shift >> i) & 1) != 1)
- i++;
- cache->i_size.way_shift = 32-i;
- }
-#if 0
- LOG_INFO("instruction cache index %d << %d, way %d << %d",
- cache->i_size.index, cache->i_size.index_shift,
- cache->i_size.way, cache->i_size.way_shift);
-
- LOG_INFO("instruction cache %d bytes %d KBytes asso %d ways",
- cache->i_size.linelen,
- cache->i_size.cachesize,
- cache->i_size.associativity);
-#endif
- /* if no l2 cache initialize l1 data cache flush function function */
- if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache == NULL) {
- armv8->armv8_mmu.armv8_cache.display_cache_info =
- armv8_handle_inner_cache_info_command;
- armv8->armv8_mmu.armv8_cache.flush_all_data_cache =
- armv8_flush_all_data;
- }
- armv8->armv8_mmu.armv8_cache.ctype = 0;
-
-done:
- dpm->finish(dpm);
- armv8_read_mpidr(target);
- return retval;
-
-}
-
int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
{
struct arm *arm = &armv8->arm;
armv8->arm.common_magic = ARM_COMMON_MAGIC;
armv8->common_magic = ARMV8_COMMON_MAGIC;
- arm->read_core_reg = armv8_read_core_reg;
-#if 0
- arm->write_core_reg = armv8_write_core_reg;
-#endif
-
armv8->armv8_mmu.armv8_cache.l2_cache = NULL;
- armv8->armv8_mmu.armv8_cache.ctype = -1;
+ armv8->armv8_mmu.armv8_cache.info = -1;
armv8->armv8_mmu.armv8_cache.flush_all_data_cache = NULL;
armv8->armv8_mmu.armv8_cache.display_cache_info = NULL;
return ERROR_OK;
if (arm->core_mode == ARM_MODE_ABT)
armv8_show_fault_registers(target);
+
if (target->debug_reason == DBG_REASON_WATCHPOINT)
LOG_USER("Watchpoint triggered at PC %#08x",
(unsigned) armv8->dpm.wp_pc);
unsigned id;
const char *name;
unsigned bits;
+ enum arm_mode mode;
enum reg_type type;
const char *group;
const char *feature;
} armv8_regs[] = {
- { ARMV8_R0, "x0", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R1, "x1", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R2, "x2", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R3, "x3", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R4, "x4", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R5, "x5", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R6, "x6", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R7, "x7", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R8, "x8", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R9, "x9", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R10, "x10", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R11, "x11", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R12, "x12", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R13, "x13", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R14, "x14", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R15, "x15", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R16, "x16", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R17, "x17", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R18, "x18", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R19, "x19", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R20, "x20", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R21, "x21", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R22, "x22", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R23, "x23", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R24, "x24", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R25, "x25", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R26, "x26", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R27, "x27", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R28, "x28", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R29, "x29", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R30, "x30", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-
- { ARMV8_R31, "sp", 64, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_PC, "pc", 64, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core" },
-
- { ARMV8_xPSR, "CPSR", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R0, "x0", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R1, "x1", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R2, "x2", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R3, "x3", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R4, "x4", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R5, "x5", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R6, "x6", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R7, "x7", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R8, "x8", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R9, "x9", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R10, "x10", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R11, "x11", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R12, "x12", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R13, "x13", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R14, "x14", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R15, "x15", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R16, "x16", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R17, "x17", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R18, "x18", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R19, "x19", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R20, "x20", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R21, "x21", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R22, "x22", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R23, "x23", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R24, "x24", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R25, "x25", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R26, "x26", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R27, "x27", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R28, "x28", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R29, "x29", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R30, "x30", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+
+ { ARMV8_SP, "sp", 64, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_PC, "pc", 64, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core" },
+
+ { ARMV8_xPSR, "CPSR", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.aarch64.core" },
+
+ { ARMV8_ELR_EL1, "ELR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked" },
+ { ARMV8_ESR_EL1, "ESR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
+ { ARMV8_SPSR_EL1, "SPSR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
+
+ { ARMV8_ELR_EL2, "ELR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked" },
+ { ARMV8_ESR_EL2, "ESR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
+ { ARMV8_SPSR_EL2, "SPSR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
+
+ { ARMV8_ELR_EL3, "ELR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked" },
+ { ARMV8_ESR_EL3, "ESR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
+ { ARMV8_SPSR_EL3, "SPSR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
};
-#define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
+static const struct {
+ unsigned id;
+ const char *name;
+ unsigned bits;
+ enum arm_mode mode;
+ enum reg_type type;
+ const char *group;
+ const char *feature;
+} armv8_regs32[] = {
+ { ARMV8_R0, "r0", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R1, "r1", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R2, "r2", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R3, "r3", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R4, "r4", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R5, "r5", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R6, "r6", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R7, "r7", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R8, "r8", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R9, "r9", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R10, "r10", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R11, "r11", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R12, "r12", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R13, "sp", 32, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_R14, "lr", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_PC, "pc", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_xPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+};
+#define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
+#define ARMV8_NUM_REGS32 ARRAY_SIZE(armv8_regs32)
static int armv8_get_core_reg(struct reg *reg)
{
- int retval;
struct arm_reg *armv8_reg = reg->arch_info;
struct target *target = armv8_reg->target;
struct arm *arm = target_to_arm(target);
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
- retval = arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
-
- return retval;
+ return arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
}
static int armv8_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct arm_reg *armv8_reg = reg->arch_info;
struct target *target = armv8_reg->target;
+ struct arm *arm = target_to_arm(target);
uint64_t value = buf_get_u64(buf, 0, 64);
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
- buf_set_u64(reg->value, 0, 64, value);
+ if (reg == arm->cpsr) {
+ armv8_set_cpsr(arm, (uint32_t)value);
+ } else {
+ buf_set_u64(reg->value, 0, 64, value);
+ reg->valid = 1;
+ }
+
reg->dirty = 1;
- reg->valid = 1;
return ERROR_OK;
}
.set = armv8_set_core_reg,
};
+static int armv8_get_core_reg32(struct reg *reg)
+{
+ struct arm_reg *armv8_reg = reg->arch_info;
+ struct target *target = armv8_reg->target;
+ struct arm *arm = target_to_arm(target);
+ struct reg_cache *cache = arm->core_cache;
+ struct reg *reg64;
+ int retval;
+
+ LOG_DEBUG("reg.name:%s number:%i arm.num:%i value:0x%08" PRIx64,
+ reg->name, reg->number, armv8_reg->num, buf_get_u64(reg->value, 0, 32));
+
+ /* get the corresponding Aarch64 register */
+ reg64 = cache->reg_list + armv8_reg->num;
+ if (reg64->valid) {
+ reg->valid = true;
+ return ERROR_OK;
+ }
+
+ retval = arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
+ if (retval == ERROR_OK)
+ reg->valid = reg64->valid;
+
+ return retval;
+}
+
+static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf)
+{
+ struct arm_reg *armv8_reg = reg->arch_info;
+ struct target *target = armv8_reg->target;
+ struct arm *arm = target_to_arm(target);
+ struct reg_cache *cache = arm->core_cache;
+ struct reg *reg64 = cache->reg_list + armv8_reg->num;
+ uint32_t value = buf_get_u32(buf, 0, 32);
+
+ if (target->state != TARGET_HALTED)
+ return ERROR_TARGET_NOT_HALTED;
+
+ if (reg64 == arm->cpsr) {
+ armv8_set_cpsr(arm, value);
+ } else {
+ buf_set_u32(reg->value, 0, 32, value);
+ reg->valid = 1;
+ reg64->valid = 1;
+ }
+
+ reg64->dirty = 1;
+
+ return ERROR_OK;
+}
+
+static const struct reg_arch_type armv8_reg32_type = {
+ .get = armv8_get_core_reg32,
+ .set = armv8_set_core_reg32,
+};
+
/** Builds cache of architecturally defined registers. */
struct reg_cache *armv8_build_reg_cache(struct target *target)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm *arm = &armv8->arm;
int num_regs = ARMV8_NUM_REGS;
+ int num_regs32 = ARMV8_NUM_REGS32;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
+ struct reg_cache *cache32 = malloc(sizeof(struct reg_cache));
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
+ struct reg *reg_list32 = calloc(num_regs32, sizeof(struct reg));
struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
struct reg_feature *feature;
int i;
/* Build the process context cache */
- cache->name = "arm v8 registers";
- cache->next = NULL;
+ cache->name = "Aarch64 registers";
+ cache->next = cache32;
cache->reg_list = reg_list;
cache->num_regs = num_regs;
- (*cache_p) = cache;
for (i = 0; i < num_regs; i++) {
arch_info[i].num = armv8_regs[i].id;
+ arch_info[i].mode = armv8_regs[i].mode;
arch_info[i].target = target;
arch_info[i].arm = arm;
reg_list[i].name = armv8_regs[i].name;
reg_list[i].size = armv8_regs[i].bits;
- reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
+ reg_list[i].value = &arch_info[i].value[0];
reg_list[i].type = &armv8_reg_type;
reg_list[i].arch_info = &arch_info[i];
arm->pc = reg_list + ARMV8_PC;
arm->core_cache = cache;
+ /* shadow cache for ARM mode registers */
+ cache32->name = "Aarch32 registers";
+ cache32->next = NULL;
+ cache32->reg_list = reg_list32;
+ cache32->num_regs = num_regs32;
+
+ for (i = 0; i < num_regs32; i++) {
+ reg_list32[i].name = armv8_regs32[i].name;
+ reg_list32[i].size = armv8_regs32[i].bits;
+ reg_list32[i].value = &arch_info[armv8_regs32[i].id].value[0];
+ reg_list32[i].type = &armv8_reg32_type;
+ reg_list32[i].arch_info = &arch_info[armv8_regs32[i].id];
+ reg_list32[i].group = armv8_regs32[i].group;
+ reg_list32[i].number = i;
+ reg_list32[i].exist = true;
+ reg_list32[i].caller_save = true;
+
+ feature = calloc(1, sizeof(struct reg_feature));
+ if (feature) {
+ feature->name = armv8_regs32[i].feature;
+ reg_list32[i].feature = feature;
+ } else
+ LOG_ERROR("unable to allocate feature list");
+
+ reg_list32[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
+ if (reg_list32[i].reg_data_type)
+ reg_list32[i].reg_data_type->type = armv8_regs32[i].type;
+ else
+ LOG_ERROR("unable to allocate reg type list");
+ }
+
+ (*cache_p) = cache;
return cache;
}
struct arm *arm = target_to_arm(target);
int i;
- switch (reg_class) {
- case REG_CLASS_GENERAL:
- case REG_CLASS_ALL:
- *reg_list_size = ARMV8_LAST_REG;
- *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
+ if (arm->core_state == ARM_STATE_AARCH64) {
- for (i = 0; i < ARMV8_LAST_REG; i++)
- (*reg_list)[i] = armv8_reg_current(arm, i);
+ LOG_DEBUG("Creating Aarch64 register list");
- return ERROR_OK;
+ switch (reg_class) {
+ case REG_CLASS_GENERAL:
+ *reg_list_size = ARMV8_ELR_EL1;
+ *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
- default:
- LOG_ERROR("not a valid register class type in query.");
- return ERROR_FAIL;
- break;
+ for (i = 0; i < *reg_list_size; i++)
+ (*reg_list)[i] = armv8_reg_current(arm, i);
+ return ERROR_OK;
+
+ case REG_CLASS_ALL:
+ *reg_list_size = ARMV8_LAST_REG;
+ *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
+
+ for (i = 0; i < *reg_list_size; i++)
+ (*reg_list)[i] = armv8_reg_current(arm, i);
+
+ return ERROR_OK;
+
+ default:
+ LOG_ERROR("not a valid register class type in query.");
+ return ERROR_FAIL;
+ }
+ } else {
+ struct reg_cache *cache32 = arm->core_cache->next;
+
+ LOG_DEBUG("Creating Aarch32 register list");
+
+ switch (reg_class) {
+ case REG_CLASS_GENERAL:
+ case REG_CLASS_ALL:
+ *reg_list_size = cache32->num_regs;
+ *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
+
+ for (i = 0; i < *reg_list_size; i++)
+ (*reg_list)[i] = cache32->reg_list + i;
+
+ return ERROR_OK;
+ default:
+ LOG_ERROR("not a valid register class type in query.");
+ return ERROR_FAIL;
+ }
}
}
projects / openocd / blobdiff