mips32, drop unnecessary code in mips32_pracc.c

[openocd] / src / target / armv8.c

diff --git a/src/target/armv8.c b/src/target/armv8.c
index 54ec42f0c42696e05e377c88d74fd4d0755b48d0..db7a8717b3dc02892483fd2fe620ec61cb7288ef 100644 (file)
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -46,11 +46,6 @@ static const char * const armv8_state_strings[] = {
 static const struct {
        const char *name;
        unsigned psr;
-       /* For user and system modes, these list indices for all registers.
-        * otherwise they're just indices for the shadow registers and SPSR.
-        */
-       unsigned short n_indices;
-       const uint8_t *indices;
 } armv8_mode_data[] = {
        /* These special modes are currently only supported
         * by ARMv6M and ARMv7M profiles */
@@ -413,8 +408,7 @@ static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t va
                break;
        case ARMV8_SP:
                retval = dpm->instr_write_data_dcc(dpm,
-                       ARMV4_5_MRC(14, 0, 13, 0, 5, 0),
-                       value);
+                               ARMV4_5_MRC(14, 0, 13, 0, 5, 0), value);
                        break;
        case ARMV8_PC:/* PC
                 * read r0 from DCC; then "MOV pc, r0" */
@@ -510,10 +504,9 @@ int armv8_read_mpidr(struct armv8_common *armv8)
                LOG_INFO("%s cluster %x core %x %s", target_name(armv8->arm.target),
                        armv8->cluster_id,
                        armv8->cpu_id,
-                       armv8->multi_processor_system == 0 ? "multi core" : "mono core");
-
+                       armv8->multi_processor_system == 0 ? "multi core" : "single core");
        } else
-               LOG_ERROR("mpdir not in multiprocessor format");
+               LOG_ERROR("mpidr not in multiprocessor format");
 
 done:
        dpm->finish(dpm);
@@ -617,7 +610,7 @@ done:
        /* (void) */ dpm->finish(dpm);
 }
 
-static void armv8_show_fault_registers(struct target *target)
+static __unused void armv8_show_fault_registers(struct target *target)
 {
        struct armv8_common *armv8 = target_to_armv8(target);
 
@@ -838,9 +831,6 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
 
        dpm->finish(dpm);
 
-       if (retval != ERROR_OK)
-               return retval;
-
        if (retval != ERROR_OK)
                return retval;
 
@@ -1091,9 +1081,6 @@ static int armv8_get_core_reg32(struct reg *reg)
        struct reg *reg64;
        int retval;
 
-       LOG_DEBUG("reg.name:%s number:%i arm.num:%i value:0x%08" PRIx64,
-                       reg->name, reg->number, armv8_reg->num, buf_get_u64(reg->value, 0, 32));
-
        /* get the corresponding Aarch64 register */
        reg64 = cache->reg_list + armv8_reg->num;
        if (reg64->valid) {
@@ -1101,7 +1088,7 @@ static int armv8_get_core_reg32(struct reg *reg)
                return ERROR_OK;
        }
 
-       retval = arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
+       retval = arm->read_core_reg(target, reg64, armv8_reg->num, arm->core_mode);
        if (retval == ERROR_OK)
                reg->valid = reg64->valid;
 
@@ -1117,9 +1104,6 @@ static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf)
        struct reg *reg64 = cache->reg_list + armv8_reg->num;
        uint32_t value = buf_get_u32(buf, 0, 32);
 
-       if (target->state != TARGET_HALTED)
-               return ERROR_TARGET_NOT_HALTED;
-
        if (reg64 == arm->cpsr) {
                armv8_set_cpsr(arm, value);
        } else {
@@ -1258,7 +1242,7 @@ int armv8_get_gdb_reg_list(struct target *target,
 
        if (arm->core_state == ARM_STATE_AARCH64) {
 
-               LOG_DEBUG("Creating Aarch64 register list");
+               LOG_DEBUG("Creating Aarch64 register list for target %s", target_name(target));
 
                switch (reg_class) {
                case REG_CLASS_GENERAL:
@@ -1285,7 +1269,7 @@ int armv8_get_gdb_reg_list(struct target *target,
        } else {
                struct reg_cache *cache32 = arm->core_cache->next;
 
-               LOG_DEBUG("Creating Aarch32 register list");
+               LOG_DEBUG("Creating Aarch32 register list for target %s", target_name(target));
 
                switch (reg_class) {
                case REG_CLASS_GENERAL:
@@ -1303,3 +1287,24 @@ int armv8_get_gdb_reg_list(struct target *target,
                }
        }
 }
+
+int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
+{
+       uint32_t tmp;
+
+       /* Read register */
+       int retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+                       armv8->debug_base + reg, &tmp);
+       if (ERROR_OK != retval)
+               return retval;
+
+       /* clear bitfield */
+       tmp &= ~mask;
+       /* put new value */
+       tmp |= value & mask;
+
+       /* write new value */
+       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+                       armv8->debug_base + reg, tmp);
+       return retval;
+}