{
int el = (dpm->dscr >> 8) & 0x3;
int rw = (dpm->dscr >> 10) & 0xF;
- int pos;
dpm->last_el = el;
- /* find the first '0' in DSCR.RW */
- for (pos = 3; pos >= 0; pos--) {
- if ((rw & (1 << pos)) == 0)
- break;
- }
-
- if (el > pos)
+ /* In Debug state, each bit gives the current Execution state of each EL */
+ if ((rw >> el) & 0b1)
return ARM_STATE_AARCH64;
return ARM_STATE_ARM;
static int dpmv8_write_dcc(struct armv8_common *armv8, uint32_t data)
{
- LOG_DEBUG("write DCC 0x%08" PRIx32, data);
return mem_ap_write_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRRX, data);
}
static int dpmv8_write_dcc_64(struct armv8_common *armv8, uint64_t data)
{
int ret;
- LOG_DEBUG("write DCC Low word 0x%08" PRIx32, (unsigned)data);
- LOG_DEBUG("write DCC High word 0x%08" PRIx32, (unsigned)(data >> 32));
ret = mem_ap_write_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRRX, data);
- ret += mem_ap_write_u32(armv8->debug_ap,
+ if (ret == ERROR_OK)
+ ret = mem_ap_write_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRTX, data >> 32);
return ret;
}
data);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
if (dscr_p)
*dscr_p = dscr;
if (retval != ERROR_OK)
return retval;
if (timeval_ms() > then + 1000) {
- LOG_ERROR("Timeout waiting for read dcc");
+ LOG_ERROR("Timeout waiting for DTR_TX_FULL, dscr = 0x%08" PRIx32, dscr);
return ERROR_FAIL;
}
}
return retval;
*data = *(uint32_t *)data | (uint64_t)higher << 32;
- LOG_DEBUG("read DCC 0x%16.16" PRIx64, *data);
if (dscr_p)
*dscr_p = dscr;
uint32_t dscr;
int retval;
- /* set up invariant: INSTR_COMP is set after ever DPM operation */
+ /* set up invariant: ITE is set after ever DPM operation */
long long then = timeval_ms();
for (;; ) {
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
uint32_t opcode, uint32_t *p_dscr)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
- uint32_t dscr = DSCR_ITE;
+ uint32_t dscr = dpm->dscr;
int retval;
- LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
-
if (p_dscr)
dscr = *p_dscr;
if (dscr & DSCR_ERR) {
LOG_ERROR("Opcode 0x%08"PRIx32", DSCR.ERR=1, DSCR.EL=%i", opcode, dpm->last_el);
- armv8_dpm_handle_exception(dpm);
+ armv8_dpm_handle_exception(dpm, true);
retval = ERROR_FAIL;
}
uint32_t opcode, uint64_t data)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
- uint32_t dscr = DSCR_ITE;
int retval;
- retval = dpmv8_write_dcc_64(armv8, data);
- if (retval != ERROR_OK)
- return retval;
+ if (dpm->arm->core_state != ARM_STATE_AARCH64)
+ return dpmv8_instr_write_data_r0(dpm, opcode, data);
- retval = dpmv8_exec_opcode(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
- if (retval != ERROR_OK)
- return retval;
+ /* transfer data from DCC to R0 */
+ retval = dpmv8_write_dcc_64(armv8, data);
+ if (retval == ERROR_OK)
+ retval = dpmv8_exec_opcode(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dpm->dscr);
/* then the opcode, taking data from R0 */
- return dpmv8_exec_opcode(dpm, opcode, &dscr);
+ if (retval == ERROR_OK)
+ retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
+
+ return retval;
}
static int dpmv8_instr_cpsr_sync(struct arm_dpm *dpm)
uint32_t opcode, uint32_t *data)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
- uint32_t dscr = DSCR_ITE;
int retval;
/* the opcode, writing data to DCC */
- retval = dpmv8_exec_opcode(dpm, opcode, &dscr);
+ retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
if (retval != ERROR_OK)
return retval;
- return dpmv8_read_dcc(armv8, data, &dscr);
+ return dpmv8_read_dcc(armv8, data, &dpm->dscr);
}
static int dpmv8_instr_read_data_dcc_64(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
- uint32_t dscr = DSCR_ITE;
int retval;
/* the opcode, writing data to DCC */
- retval = dpmv8_exec_opcode(dpm, opcode, &dscr);
+ retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
if (retval != ERROR_OK)
return retval;
- return dpmv8_read_dcc_64(armv8, data, &dscr);
+ return dpmv8_read_dcc_64(armv8, data, &dpm->dscr);
}
static int dpmv8_instr_read_data_r0(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
- uint32_t dscr = DSCR_ITE;
int retval;
/* the opcode, writing data to R0 */
- retval = dpmv8_exec_opcode(dpm, opcode, &dscr);
+ retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
if (retval != ERROR_OK)
return retval;
/* write R0 to DCC */
- retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, WRITE_REG_DTRTX), &dscr);
+ retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, WRITE_REG_DTRTX), &dpm->dscr);
if (retval != ERROR_OK)
return retval;
- return dpmv8_read_dcc(armv8, data, &dscr);
+ return dpmv8_read_dcc(armv8, data, &dpm->dscr);
}
static int dpmv8_instr_read_data_r0_64(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
- uint32_t dscr = DSCR_ITE;
int retval;
+ if (dpm->arm->core_state != ARM_STATE_AARCH64) {
+ uint32_t tmp;
+ retval = dpmv8_instr_read_data_r0(dpm, opcode, &tmp);
+ if (retval == ERROR_OK)
+ *data = tmp;
+ return retval;
+ }
+
/* the opcode, writing data to R0 */
- retval = dpmv8_exec_opcode(dpm, opcode, &dscr);
+ retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
if (retval != ERROR_OK)
return retval;
/* write R0 to DCC */
- retval = dpmv8_exec_opcode(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
+ retval = dpmv8_exec_opcode(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), &dpm->dscr);
if (retval != ERROR_OK)
return retval;
- return dpmv8_read_dcc_64(armv8, data, &dscr);
+ return dpmv8_read_dcc_64(armv8, data, &dpm->dscr);
}
#if 0
return retval;
}
-static int dpmv8_mrs(struct target *target, uint32_t op0,
- uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
- uint32_t *value)
-{
- struct arm *arm = target_to_arm(target);
- struct arm_dpm *dpm = arm->dpm;
- int retval;
- uint32_t op_code;
-
- retval = dpm->prepare(dpm);
- if (retval != ERROR_OK)
- return retval;
- op_code = ((op0 & 0x3) << 19 | (op1 & 0x7) << 16 | (CRn & 0xF) << 12 |\
- (CRm & 0xF) << 8 | (op2 & 0x7) << 5);
- op_code >>= 5;
- LOG_DEBUG("MRS p%d, %d, r0, c%d, c%d, %d", (int)op0,
- (int) op1, (int) CRn,
- (int) CRm, (int) op2);
- /* read coprocessor register into R0; return via DCC */
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(op_code, 0),
- value);
-
- /* (void) */ dpm->finish(dpm);
- return retval;
-}
-
-static int dpmv8_msr(struct target *target, uint32_t op0,
- uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
- uint32_t value)
-{
- struct arm *arm = target_to_arm(target);
- struct arm_dpm *dpm = arm->dpm;
- int retval;
- uint32_t op_code;
-
- retval = dpm->prepare(dpm);
- if (retval != ERROR_OK)
- return retval;
-
- op_code = ((op0 & 0x3) << 19 | (op1 & 0x7) << 16 | (CRn & 0xF) << 12 |\
- (CRm & 0xF) << 8 | (op2 & 0x7) << 5);
- op_code >>= 5;
- LOG_DEBUG("MSR p%d, %d, r0, c%d, c%d, %d", (int)op0,
- (int) op1, (int) CRn,
- (int) CRm, (int) op2);
-
- /* read DCC into r0; then write coprocessor register from R0 */
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP(op_code, 0),
- value);
-
- /* (void) */ dpm->finish(dpm);
- return retval;
-}
-
/*----------------------------------------------------------------------*/
/*
} else {
LOG_DEBUG("setting mode 0x%"PRIx32, mode);
-
- /* else force to the specified mode */
- if (is_arm_mode(mode))
- cpsr = mode;
- else
- cpsr = mode >> 4;
+ cpsr = mode;
}
switch (cpsr & 0x1f) {
armv8_opcode(armv8, ARMV8_OPC_DCPS) | target_el);
/* DCPS clobbers registers just like an exception taken */
- armv8_dpm_handle_exception(dpm);
+ armv8_dpm_handle_exception(dpm, false);
} else {
core_state = armv8_dpm_get_core_state(dpm);
if (core_state != ARM_STATE_AARCH64) {
static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
- uint64_t value_64;
- int retval;
+ int retval = ERROR_FAIL;
+
+ if (r->size <= 64) {
+ uint64_t value_64;
+ retval = armv8->read_reg_u64(armv8, regnum, &value_64);
+
+ if (retval == ERROR_OK) {
+ r->valid = true;
+ r->dirty = false;
+ buf_set_u64(r->value, 0, r->size, value_64);
+ if (r->size == 64)
+ LOG_DEBUG("READ: %s, %16.8llx", r->name, (unsigned long long) value_64);
+ else
+ LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned int) value_64);
+ }
+ } else if (r->size <= 128) {
+ uint64_t lvalue = 0, hvalue = 0;
+ retval = armv8->read_reg_u128(armv8, regnum, &lvalue, &hvalue);
- retval = armv8->read_reg_u64(armv8, regnum, &value_64);
+ if (retval == ERROR_OK) {
+ r->valid = true;
+ r->dirty = false;
- if (retval == ERROR_OK) {
- r->valid = true;
- r->dirty = false;
- buf_set_u64(r->value, 0, r->size, value_64);
- if (r->size == 64)
- LOG_DEBUG("READ: %s, %16.8llx", r->name, (unsigned long long) value_64);
- else
- LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned int) value_64);
+ buf_set_u64(r->value, 0, 64, lvalue);
+ buf_set_u64(r->value + 8, 0, r->size - 64, hvalue);
+
+ LOG_DEBUG("READ: %s, lvalue=%16.8llx", r->name, (unsigned long long) lvalue);
+ LOG_DEBUG("READ: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue);
+ }
}
- return ERROR_OK;
+ return retval;
}
/*
{
struct armv8_common *armv8 = dpm->arm->arch_info;
int retval = ERROR_FAIL;
- uint64_t value_64;
- value_64 = buf_get_u64(r->value, 0, r->size);
+ if (r->size <= 64) {
+ uint64_t value_64;
+
+ value_64 = buf_get_u64(r->value, 0, r->size);
+ retval = armv8->write_reg_u64(armv8, regnum, value_64);
+
+ if (retval == ERROR_OK) {
+ r->dirty = false;
+ if (r->size == 64)
+ LOG_DEBUG("WRITE: %s, %16.8llx", r->name, (unsigned long long)value_64);
+ else
+ LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned int)value_64);
+ }
+ } else if (r->size <= 128) {
+ uint64_t lvalue, hvalue;
+
+ lvalue = buf_get_u64(r->value, 0, 64);
+ hvalue = buf_get_u64(r->value + 8, 0, r->size - 64);
+ retval = armv8->write_reg_u128(armv8, regnum, lvalue, hvalue);
+
+ if (retval == ERROR_OK) {
+ r->dirty = false;
- retval = armv8->write_reg_u64(armv8, regnum, value_64);
- if (retval == ERROR_OK) {
- r->dirty = false;
- if (r->size == 64)
- LOG_DEBUG("WRITE: %s, %16.8llx", r->name, (unsigned long long)value_64);
- else
- LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned int)value_64);
+ LOG_DEBUG("WRITE: %s, lvalue=%16.8llx", r->name, (unsigned long long) lvalue);
+ LOG_DEBUG("WRITE: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue);
+ }
}
- return ERROR_OK;
+ return retval;
}
/**
cache = arm->core_cache;
/* read R0 first (it's used for scratch), then CPSR */
- r = cache->reg_list + 0;
+ r = cache->reg_list + ARMV8_R0;
if (!r->valid) {
- retval = dpmv8_read_reg(dpm, r, 0);
+ retval = dpmv8_read_reg(dpm, r, ARMV8_R0);
if (retval != ERROR_OK)
goto fail;
}
r->dirty = true;
+ /* read R1, too, it will be clobbered during memory access */
+ r = cache->reg_list + ARMV8_R1;
+ if (!r->valid) {
+ retval = dpmv8_read_reg(dpm, r, ARMV8_R1);
+ if (retval != ERROR_OK)
+ goto fail;
+ }
+
/* read cpsr to r0 and get it back */
retval = dpm->instr_read_data_r0(dpm,
armv8_opcode(armv8, READ_REG_DSPSR), &cpsr);
/* update core mode and state */
armv8_set_cpsr(arm, cpsr);
- for (unsigned int i = 1; i < cache->num_regs ; i++) {
+ for (unsigned int i = ARMV8_PC; i < cache->num_regs ; i++) {
struct arm_reg *arm_reg;
r = armv8_reg_current(arm, i);
if (r->valid)
continue;
+ /* Skip reading FP-SIMD registers */
+ if (r->number >= ARMV8_V0 && r->number <= ARMV8_FPCR)
+ continue;
+
/*
* Only read registers that are available from the
* current EL (or core mode).
/* ?? */
break;
default:
- LOG_DEBUG("Unknow core_state");
+ LOG_DEBUG("Unknown core_state");
break;
}
dpm->wp_pc = addr;
* This function must not perform any actions that trigger another exception
* or a recursion will happen.
*/
-void armv8_dpm_handle_exception(struct arm_dpm *dpm)
+void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
struct reg_cache *cache = dpm->arm->core_cache;
core_state = armv8_dpm_get_core_state(dpm);
armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64);
armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64);
+
+ if (do_restore)
+ armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
}
/*----------------------------------------------------------------------*/
/* coprocessor access setup */
arm->mrc = dpmv8_mrc;
arm->mcr = dpmv8_mcr;
- arm->mrs = dpmv8_mrs;
- arm->msr = dpmv8_msr;
dpm->prepare = dpmv8_dpm_prepare;
dpm->finish = dpmv8_dpm_finish;
projects / openocd / blobdiff