uint32_t count, uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval = ERROR_COMMAND_SYNTAX_ERROR;
- uint8_t apsel = swjdp->apsel;
+
LOG_DEBUG("Reading memory at real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32,
address, size, count);
if (count && buffer) {
-
- if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
-
- /* read memory through AHB-AP */
- retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap, buffer, size, count, address);
- } else {
-
- /* read memory through APB-AP */
- if (!armv7a->is_armv7r) {
- /* disable mmu */
- retval = cortex_a_mmu_modify(target, 0);
- if (retval != ERROR_OK)
- return retval;
- }
- retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
+ /* read memory through APB-AP */
+ if (!armv7a->is_armv7r) {
+ /* disable mmu */
+ retval = cortex_a_mmu_modify(target, 0);
+ if (retval != ERROR_OK)
+ return retval;
}
+ retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
}
return retval;
}
uint32_t count, const uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval = ERROR_COMMAND_SYNTAX_ERROR;
- uint8_t apsel = swjdp->apsel;
LOG_DEBUG("Writing memory to real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
size, count);
if (count && buffer) {
-
- if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
-
- /* write memory through AHB-AP */
- retval = mem_ap_sel_write_buf(swjdp, armv7a->memory_ap, buffer, size, count, address);
- } else {
-
- /* write memory through APB-AP */
- if (!armv7a->is_armv7r) {
- retval = cortex_a_mmu_modify(target, 0);
- if (retval != ERROR_OK)
- return retval;
- }
- return cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
+ /* write memory through APB-AP */
+ if (!armv7a->is_armv7r) {
+ retval = cortex_a_mmu_modify(target, 0);
+ if (retval != ERROR_OK)
+ return retval;
}
+ return cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
}
-
/* REVISIT this op is generic ARMv7-A/R stuff */
if (retval == ERROR_OK && target->state == TARGET_HALTED) {
struct arm_dpm *dpm = armv7a->arm.dpm;
LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg);
armv7a->arm.core_type = ARM_MODE_MON;
- retval = cortex_a_dpm_setup(cortex_a, didr);
- if (retval != ERROR_OK)
- return retval;
+
+ /* Avoid recreating the registers cache */
+ if (!target_was_examined(target)) {
+ retval = cortex_a_dpm_setup(cortex_a, didr);
+ if (retval != ERROR_OK)
+ return retval;
+ }
/* Setup Breakpoint Register Pairs */
cortex_a->brp_num = ((didr >> 24) & 0x0F) + 1;
return cortex_a_init_arch_info(target, cortex_a, target->tap);
}
+static void cortex_a_deinit_target(struct target *target)
+{
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+ struct arm_dpm *dpm = &cortex_a->armv7a_common.dpm;
+
+ free(cortex_a->brp_list);
+ free(dpm->dbp);
+ free(dpm->dwp);
+ free(cortex_a);
+}
static int cortex_a_mmu(struct target *target, int *enabled)
{
.target_create = cortex_a_target_create,
.init_target = cortex_a_init_target,
.examine = cortex_a_examine,
+ .deinit_target = cortex_a_deinit_target,
.read_phys_memory = cortex_a_read_phys_memory,
.write_phys_memory = cortex_a_write_phys_memory,
.target_create = cortex_r4_target_create,
.init_target = cortex_a_init_target,
.examine = cortex_a_examine,
+ .deinit_target = cortex_a_deinit_target,
};