cortex_a: remove cache handlers from cortex_a_write_phys_memory

[openocd] / src / target / cortex_a.c

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index d0260daebcda51bb3c23de5afd51b747314f528e..3da58701d869089b9480a5bc7392312db43c3247 100644 (file)
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2611,29 +2611,20 @@ static int cortex_a_read_phys_memory(struct target *target,
        uint32_t count, uint8_t *buffer)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
-       struct adiv5_dap *swjdp = armv7a->arm.dap;
        int retval = ERROR_COMMAND_SYNTAX_ERROR;
-       uint8_t apsel = swjdp->apsel;
+
        LOG_DEBUG("Reading memory at real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32,
                address, size, count);
 
        if (count && buffer) {
-
-               if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
-
-                       /* read memory through AHB-AP */
-                       retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap, buffer, size, count, address);
-               } else {
-
-                       /* read memory through APB-AP */
-                       if (!armv7a->is_armv7r) {
-                               /*  disable mmu */
-                               retval = cortex_a_mmu_modify(target, 0);
-                               if (retval != ERROR_OK)
-                                       return retval;
-                       }
-                       retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
+               /* read memory through APB-AP */
+               if (!armv7a->is_armv7r) {
+                       /*  disable mmu */
+                       retval = cortex_a_mmu_modify(target, 0);
+                       if (retval != ERROR_OK)
+                               return retval;
                }
+               retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
        }
        return retval;
 }
@@ -2692,84 +2683,19 @@ static int cortex_a_write_phys_memory(struct target *target,
        uint32_t count, const uint8_t *buffer)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
-       struct adiv5_dap *swjdp = armv7a->arm.dap;
        int retval = ERROR_COMMAND_SYNTAX_ERROR;
-       uint8_t apsel = swjdp->apsel;
 
        LOG_DEBUG("Writing memory to real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
                size, count);
 
        if (count && buffer) {
-
-               if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
-
-                       /* write memory through AHB-AP */
-                       retval = mem_ap_sel_write_buf(swjdp, armv7a->memory_ap, buffer, size, count, address);
-               } else {
-
-                       /* write memory through APB-AP */
-                       if (!armv7a->is_armv7r) {
-                               retval = cortex_a_mmu_modify(target, 0);
-                               if (retval != ERROR_OK)
-                                       return retval;
-                       }
-                       return cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
-               }
-       }
-
-
-       /* REVISIT this op is generic ARMv7-A/R stuff */
-       if (retval == ERROR_OK && target->state == TARGET_HALTED) {
-               struct arm_dpm *dpm = armv7a->arm.dpm;
-
-               retval = dpm->prepare(dpm);
-               if (retval != ERROR_OK)
-                       return retval;
-
-               /* The Cache handling will NOT work with MMU active, the
-                * wrong addresses will be invalidated!
-                *
-                * For both ICache and DCache, walk all cache lines in the
-                * address range. Cortex-A has fixed 64 byte line length.
-                *
-                * REVISIT per ARMv7, these may trigger watchpoints ...
-                */
-
-               /* invalidate I-Cache */
-               if (armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) {
-                       /* ICIMVAU - Invalidate Cache single entry
-                        * with MVA to PoU
-                        *      MCR p15, 0, r0, c7, c5, 1
-                        */
-                       for (uint32_t cacheline = 0;
-                               cacheline < size * count;
-                               cacheline += 64) {
-                               retval = dpm->instr_write_data_r0(dpm,
-                                               ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
-                                               address + cacheline);
-                               if (retval != ERROR_OK)
-                                       return retval;
-                       }
-               }
-
-               /* invalidate D-Cache */
-               if (armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) {
-                       /* DCIMVAC - Invalidate data Cache line
-                        * with MVA to PoC
-                        *      MCR p15, 0, r0, c7, c6, 1
-                        */
-                       for (uint32_t cacheline = 0;
-                               cacheline < size * count;
-                               cacheline += 64) {
-                               retval = dpm->instr_write_data_r0(dpm,
-                                               ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
-                                               address + cacheline);
-                               if (retval != ERROR_OK)
-                                       return retval;
-                       }
+               /* write memory through APB-AP */
+               if (!armv7a->is_armv7r) {
+                       retval = cortex_a_mmu_modify(target, 0);
+                       if (retval != ERROR_OK)
+                               return retval;
                }
-
-               /* (void) */ dpm->finish(dpm);
+               return cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
        }
 
        return retval;
@@ -3121,6 +3047,16 @@ static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
        return cortex_a_init_arch_info(target, cortex_a, target->tap);
 }
 
+static void cortex_a_deinit_target(struct target *target)
+{
+       struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+       struct arm_dpm *dpm = &cortex_a->armv7a_common.dpm;
+
+       free(cortex_a->brp_list);
+       free(dpm->dbp);
+       free(dpm->dwp);
+       free(cortex_a);
+}
 
 static int cortex_a_mmu(struct target *target, int *enabled)
 {
@@ -3365,6 +3301,7 @@ struct target_type cortexa_target = {
        .target_create = cortex_a_target_create,
        .init_target = cortex_a_init_target,
        .examine = cortex_a_examine,
+       .deinit_target = cortex_a_deinit_target,
 
        .read_phys_memory = cortex_a_read_phys_memory,
        .write_phys_memory = cortex_a_write_phys_memory,
@@ -3449,4 +3386,5 @@ struct target_type cortexr4_target = {
        .target_create = cortex_r4_target_create,
        .init_target = cortex_a_init_target,
        .examine = cortex_a_examine,
+       .deinit_target = cortex_a_deinit_target,
 };