arm_adi_v5: error propagation fixes

[openocd] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index f15417924332dbc121e22ca37fb42da41cdebe2e..933b42e4ce004719a4c0bbec3129909efe2edf43 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -473,7 +473,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
        return cortex_a8_read_dcc(a8, data, &dscr);
 }
 
-static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
+static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
                uint32_t addr, uint32_t control)
 {
        struct cortex_a8_common *a8 = dpm_to_a8(dpm);
@@ -481,7 +481,7 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
        uint32_t cr = a8->armv7a_common.debug_base;
        int retval;
 
-       switch (index) {
+       switch (index_t) {
        case 0 ... 15:          /* breakpoints */
                vr += CPUDBG_BVR_BASE;
                cr += CPUDBG_BCR_BASE;
@@ -489,13 +489,13 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
        case 16 ... 31:         /* watchpoints */
                vr += CPUDBG_WVR_BASE;
                cr += CPUDBG_WCR_BASE;
-               index -= 16;
+               index_t -= 16;
                break;
        default:
                return ERROR_FAIL;
        }
-       vr += 4 * index;
-       cr += 4 * index;
+       vr += 4 * index_t;
+       cr += 4 * index_t;
 
        LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
                        (unsigned) vr, (unsigned) cr);
@@ -509,23 +509,23 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
        return retval;
 }
 
-static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index)
+static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
 {
        struct cortex_a8_common *a8 = dpm_to_a8(dpm);
        uint32_t cr;
 
-       switch (index) {
+       switch (index_t) {
        case 0 ... 15:
                cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
                break;
        case 16 ... 31:
                cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
-               index -= 16;
+               index_t -= 16;
                break;
        default:
                return ERROR_FAIL;
        }
-       cr += 4 * index;
+       cr += 4 * index_t;
 
        LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
 
@@ -1523,8 +1523,14 @@ static int cortex_a8_examine_first(struct target *target)
        /* We do one extra read to ensure DAP is configured,
         * we call ahbap_debugport_init(swjdp) instead
         */
-       ahbap_debugport_init(swjdp);
-       mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
+       retval = ahbap_debugport_init(swjdp);
+       if (retval != ERROR_OK)
+               return retval;
+
+       retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
+       if (retval != ERROR_OK)
+               return retval;
+
        if ((retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
        {
@@ -1559,7 +1565,9 @@ static int cortex_a8_examine_first(struct target *target)
        LOG_DEBUG("didr = 0x%08" PRIx32, didr);
 
        armv7a->armv4_5_common.core_type = ARM_MODE_MON;
-       cortex_a8_dpm_setup(cortex_a8, didr);
+       retval = cortex_a8_dpm_setup(cortex_a8, didr);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* Setup Breakpoint Register Pairs */
        cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
@@ -1801,10 +1809,7 @@ static int cortex_a8_mmu(struct target *target, int *enabled)
 static int cortex_a8_virt2phys(struct target *target,
                uint32_t virt, uint32_t *phys)
 {
-       int type;
        uint32_t cb;
-       int domain;
-       uint32_t ap;
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
        // struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
        struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -1819,7 +1824,7 @@ static int cortex_a8_virt2phys(struct target *target,
         cortex_a8->current_address_mode = ARM_MODE_SVC;
        uint32_t ret;
        int retval = armv4_5_mmu_translate_va(target,
-                       &armv7a->armv4_5_mmu, virt, &type, &cb, &domain, &ap, &ret);
+                       &armv7a->armv4_5_mmu, virt, &cb, &ret);
        if (retval != ERROR_OK)
                return retval;
     /* Reset the flag. We don't want someone else to use it by error */
@@ -1842,10 +1847,13 @@ COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
 COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
 {
        struct target *target = get_current_target(CMD_CTX);
+       if (!target_was_examined(target))
+       {
+               LOG_ERROR("target not examined yet");
+               return ERROR_FAIL;
+       }
 
-       cortex_a8_init_debug_access(target);
-
-       return ERROR_OK;
+       return cortex_a8_init_debug_access(target);
 }
 
 static const struct command_registration cortex_a8_exec_command_handlers[] = {