ARM ADIv5: rename more JTAG-specific routines

[openocd] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 424263d0cbdb926e3b7dd7134454463314ec20d7..f4818f8d0f2146a81a5869bb4df5890bd76f1ad1 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -53,7 +53,9 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
                uint32_t value, int regnum);
 /*
  * FIXME do topology discovery using the ROM; don't
- * assume this is an OMAP3.
+ * assume this is an OMAP3.   Also, allow for multiple ARMv7-A
+ * cores, with different AP numbering ... don't use a #define
+ * for these numbers, use per-core armv7a state.
  */
 #define swjdp_memoryap 0
 #define swjdp_debugap 1
@@ -695,9 +697,7 @@ static int cortex_a8_resume(struct target *target, int current,
 #endif
 
        /* current = 1: continue on current pc, otherwise continue at <address> */
-       resume_pc = buf_get_u32(
-                       armv4_5->core_cache->reg_list[15].value,
-                       0, 32);
+       resume_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
        if (!current)
                resume_pc = address;
 
@@ -721,10 +721,9 @@ static int cortex_a8_resume(struct target *target, int current,
                return ERROR_FAIL;
        }
        LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
-       buf_set_u32(armv4_5->core_cache->reg_list[15].value,
-                       0, 32, resume_pc);
-       armv4_5->core_cache->reg_list[15].dirty = 1;
-       armv4_5->core_cache->reg_list[15].valid = 1;
+       buf_set_u32(armv4_5->pc->value, 0, 32, resume_pc);
+       armv4_5->pc->dirty = 1;
+       armv4_5->pc->valid = 1;
 
        cortex_a8_restore_context(target, handle_breakpoints);
 
@@ -869,7 +868,7 @@ static int cortex_a8_debug_entry(struct target *target)
                        regfile[ARM_PC] -= 8;
                }
 
-               reg = armv4_5->core_cache->reg_list + 15;
+               reg = armv4_5->pc;
                buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
                reg->dirty = reg->valid;
        }
@@ -952,7 +951,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
        }
 
        /* current = 1: continue on current pc, otherwise continue at <address> */
-       r = armv4_5->core_cache->reg_list + 15;
+       r = armv4_5->pc;
        if (!current)
        {
                buf_set_u32(r->value, 0, 32, address);
@@ -1461,7 +1460,8 @@ static int cortex_a8_examine_first(struct target *target)
        int retval = ERROR_OK;
        uint32_t didr, ctypr, ttypr, cpuid;
 
-       LOG_DEBUG("TODO");
+       /* stop assuming this is an OMAP! */
+       LOG_DEBUG("TODO - autoconfigure");
 
        /* Here we shall insert a proper ROM Table scan */
        armv7a->debug_base = OMAP3530_DEBUG_BASE;
@@ -1474,28 +1474,28 @@ static int cortex_a8_examine_first(struct target *target)
        if ((retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
        {
-               LOG_DEBUG("Examine failed");
+               LOG_DEBUG("Examine %s failed", "CPUID");
                return retval;
        }
 
        if ((retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
        {
-               LOG_DEBUG("Examine failed");
+               LOG_DEBUG("Examine %s failed", "CTYPR");
                return retval;
        }
 
        if ((retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
        {
-               LOG_DEBUG("Examine failed");
+               LOG_DEBUG("Examine %s failed", "TTYPR");
                return retval;
        }
 
        if ((retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
        {
-               LOG_DEBUG("Examine failed");
+               LOG_DEBUG("Examine %s failed", "DIDR");
                return retval;
        }
 
@@ -1572,9 +1572,7 @@ static int cortex_a8_init_arch_info(struct target *target,
        cortex_a8->jtag_info.tap = tap;
        cortex_a8->jtag_info.scann_size = 4;
 
-       swjdp->dp_select_value = -1;
-       swjdp->ap_csw_value = -1;
-       swjdp->ap_tar_value = -1;
+       /* Leave (only) generic DAP stuff for debugport_init() */
        swjdp->jtag_info = &cortex_a8->jtag_info;
        swjdp->memaccess_tck = 80;
 
@@ -1642,13 +1640,13 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
 static const struct command_registration cortex_a8_exec_command_handlers[] = {
        {
                .name = "cache_info",
-               .handler = &cortex_a8_handle_cache_info_command,
+               .handler = cortex_a8_handle_cache_info_command,
                .mode = COMMAND_EXEC,
                .help = "display information about target caches",
        },
        {
                .name = "dbginit",
-               .handler = &cortex_a8_handle_dbginit_command,
+               .handler = cortex_a8_handle_dbginit_command,
                .mode = COMMAND_EXEC,
                .help = "Initialize core debug",
        },