armv7m: use consistent arm.cpsr member

[openocd] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index c436bad482a592431fa6b8c1d30b6125b2bbd62c..fbe635bdd8bc695bfe90b49f5e27cd4389179c49 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -21,7 +21,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  *                                                                         *
  *                                                                         *
  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
@@ -430,7 +430,7 @@ static int cortex_m3_debug_entry(struct target *target)
                        arm->read_core_reg(target, r, i, ARM_MODE_ANY);
        }
 
-       r = arm->core_cache->reg_list + ARMV7M_xPSR;
+       r = arm->cpsr;
        xPSR = buf_get_u32(r->value, 0, 32);
 
 #ifdef ARMV7_GDB_HACKS
@@ -632,6 +632,12 @@ static int cortex_m3_soft_reset_halt(struct target *target)
        uint32_t dcb_dhcsr = 0;
        int retval, timeout = 0;
 
+       /* soft_reset_halt is deprecated on cortex_m as the same functionality
+        * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
+        * As this reset only used VC_CORERESET it would only ever reset the cortex_m
+        * core, not the peripherals */
+       LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
+
        /* Enter debug state on reset; restore DEMCR in endreset_event() */
        retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
                        TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
@@ -726,7 +732,7 @@ static int cortex_m3_resume(struct target *target, int current,
                r->valid = true;
 
                /* Make sure we are in Thumb mode */
-               r = armv7m->arm.core_cache->reg_list + ARMV7M_xPSR;
+               r = armv7m->arm.cpsr;
                buf_set_u32(r->value, 24, 1, 1);
                r->dirty = true;
                r->valid = true;
@@ -989,7 +995,8 @@ static int cortex_m3_assert_reset(struct target *target)
 
        bool srst_asserted = false;
 
-       if (jtag_reset_config & RESET_SRST_NO_GATING) {
+       if ((jtag_reset_config & RESET_HAS_SRST) &&
+           (jtag_reset_config & RESET_SRST_NO_GATING)) {
                adapter_assert_reset();
                srst_asserted = true;
        }
@@ -1060,11 +1067,11 @@ static int cortex_m3_assert_reset(struct target *target)
                if (retval != ERROR_OK)
                        return retval;
 
-               LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
+               LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
                        ? "SYSRESETREQ" : "VECTRESET");
 
                if (reset_config == CORTEX_M3_RESET_VECTRESET) {
-                       LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
+                       LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
                                "handler to reset any peripherals or configure hardware srst support.");
                }
 
@@ -1796,6 +1803,9 @@ fail1:
                for (j = 0; j < 3; j++, reg++)
                        cortex_m3_dwt_addreg(target, cache->reg_list + reg,
                                dwt_comp + 3 * i + j);
+
+               /* make sure we clear any watchpoints enabled on the target */
+               target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
        }
 
        *register_get_last_cache_p(&target->reg_cache) = cache;
@@ -1887,6 +1897,9 @@ int cortex_m3_examine(struct target *target)
                        cortex_m3->fp_comparator_list[i].type =
                                (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
                        cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
+
+                       /* make sure we clear any breakpoints enabled on the target */
+                       target_write_u32(target, cortex_m3->fp_comparator_list[i].fpcr_address, 0);
                }
                LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
                        fpcr,
@@ -2044,7 +2057,7 @@ static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
        struct cortex_m3_common *cm3)
 {
        if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
-               command_print(cmd_ctx, "target is not a Cortex-M3");
+               command_print(cmd_ctx, "target is not a Cortex-M");
                return ERROR_TARGET_INVALID;
        }
        return ERROR_OK;
@@ -2179,7 +2192,7 @@ COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
        }
 
        n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode);
-       command_print(CMD_CTX, "cortex_m3 interrupt mask %s", n->name);
+       command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
 
        return ERROR_OK;
 }
@@ -2216,7 +2229,7 @@ COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
                        break;
        }
 
-       command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
+       command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
 
        return ERROR_OK;
 }
@@ -2226,7 +2239,7 @@ static const struct command_registration cortex_m3_exec_command_handlers[] = {
                .name = "maskisr",
                .handler = handle_cortex_m3_mask_interrupts_command,
                .mode = COMMAND_EXEC,
-               .help = "mask cortex_m3 interrupts",
+               .help = "mask cortex_m interrupts",
                .usage = "['auto'|'on'|'off']",
        },
        {
@@ -2250,9 +2263,9 @@ static const struct command_registration cortex_m3_command_handlers[] = {
                .chain = armv7m_command_handlers,
        },
        {
-               .name = "cortex_m3",
+               .name = "cortex_m",
                .mode = COMMAND_EXEC,
-               .help = "Cortex-M3 command group",
+               .help = "Cortex-M command group",
                .usage = "",
                .chain = cortex_m3_exec_command_handlers,
        },
@@ -2260,7 +2273,8 @@ static const struct command_registration cortex_m3_command_handlers[] = {
 };
 
 struct target_type cortexm3_target = {
-       .name = "cortex_m3",
+       .name = "cortex_m",
+       .deprecated_name = "cortex_m3",
 
        .poll = cortex_m3_poll,
        .arch_state = armv7m_arch_state,