return ERROR_OK;
}
+/* PSP is used in some thread modes */
+static const int armv7m_psp_reg_map[17] = {
+ ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
+ ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
+ ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
+ ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
+ ARMV7M_xPSR,
+};
+
+/* MSP is used in handler and some thread modes */
+static const int armv7m_msp_reg_map[17] = {
+ ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
+ ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
+ ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
+ ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
+ ARMV7M_xPSR,
+};
+
static int cortex_m3_debug_entry(struct target *target)
{
int i;
int retval;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
+ struct arm *arm = &armv7m->arm;
struct swjdp_common *swjdp = &armv7m->swjdp_info;
struct reg *r;
{
armv7m->core_mode = ARMV7M_MODE_HANDLER;
armv7m->exception_number = (xPSR & 0x1FF);
+
+ arm->core_mode = ARM_MODE_HANDLER;
+ arm->map = armv7m_msp_reg_map;
}
else
{
- armv7m->core_mode = buf_get_u32(armv7m->core_cache
- ->reg_list[ARMV7M_CONTROL].value, 0, 1);
+ unsigned control = buf_get_u32(armv7m->core_cache
+ ->reg_list[ARMV7M_CONTROL].value, 0, 2);
+
+ /* is this thread privileged? */
+ armv7m->core_mode = control & 1;
+ arm->core_mode = armv7m->core_mode
+ ? ARM_MODE_USER_THREAD
+ : ARM_MODE_THREAD;
+
+ /* which stack is it using? */
+ if (control & 2)
+ arm->map = armv7m_psp_reg_map;
+ else
+ arm->map = armv7m_msp_reg_map;
+
armv7m->exception_number = 0;
}
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
armv7m_mode_strings[armv7m->core_mode],
- *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
+ *(uint32_t*)(arm->pc->value),
target_state_name(target));
if (armv7m->post_debug_entry)
}
/* current = 1: continue on current pc, otherwise continue at <address> */
- r = armv7m->core_cache->reg_list + 15;
+ r = armv7m->arm.pc;
if (!current)
{
buf_set_u32(r->value, 0, 32, address);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
struct swjdp_common *swjdp = &armv7m->swjdp_info;
struct breakpoint *breakpoint = NULL;
- struct reg *pc = armv7m->core_cache->reg_list + 15;
+ struct reg *pc = armv7m->arm.pc;
bool bkpt_inst_found = false;
if (target->state != TARGET_HALTED)
cortex_m3->jtag_info.tap = tap;
cortex_m3->jtag_info.scann_size = 4;
- armv7m->swjdp_info.dp_select_value = -1;
- armv7m->swjdp_info.ap_csw_value = -1;
- armv7m->swjdp_info.ap_tar_value = -1;
+ /* Leave (only) generic DAP stuff for debugport_init(); */
armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
armv7m->swjdp_info.memaccess_tck = 8;
- armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
+ /* Cortex-M3 has 4096 bytes autoincrement range */
+ armv7m->swjdp_info.tar_autoincr_block = (1 << 12);
/* register arch-specific functions */
armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;