ADIv5 clean up AP selection and register caching

[openocd] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index fbc879f1b9a2339f69ccf3c684b14a8d9460c4c3..3dd9468594acf17844b69761a00a56f5aefd41be 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -427,7 +427,7 @@ static int cortex_m3_debug_entry(struct target *target)
 
        LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
                armv7m_mode_strings[armv7m->core_mode],
-               *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
+               *(uint32_t*)(arm->pc->value),
                target_state_name(target));
 
        if (armv7m->post_debug_entry)
@@ -680,7 +680,7 @@ static int cortex_m3_resume(struct target *target, int current,
        }
 
        /* current = 1: continue on current pc, otherwise continue at <address> */
-       r = armv7m->core_cache->reg_list + 15;
+       r = armv7m->arm.pc;
        if (!current)
        {
                buf_set_u32(r->value, 0, 32, address);
@@ -749,7 +749,7 @@ static int cortex_m3_step(struct target *target, int current,
        struct armv7m_common *armv7m = &cortex_m3->armv7m;
        struct swjdp_common *swjdp = &armv7m->swjdp_info;
        struct breakpoint *breakpoint = NULL;
-       struct reg *pc = armv7m->core_cache->reg_list + 15;
+       struct reg *pc = armv7m->arm.pc;
        bool bkpt_inst_found = false;
 
        if (target->state != TARGET_HALTED)
@@ -1848,12 +1848,11 @@ static int cortex_m3_init_arch_info(struct target *target,
        cortex_m3->jtag_info.tap = tap;
        cortex_m3->jtag_info.scann_size = 4;
 
-       armv7m->swjdp_info.dp_select_value = -1;
-       armv7m->swjdp_info.ap_csw_value = -1;
-       armv7m->swjdp_info.ap_tar_value = -1;
+       /* Leave (only) generic DAP stuff for debugport_init(); */
        armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
        armv7m->swjdp_info.memaccess_tck = 8;
-       armv7m->swjdp_info.tar_autoincr_block = (1 << 12);      /* Cortex-M3 has 4096 bytes autoincrement range */
+       /* Cortex-M3 has 4096 bytes autoincrement range */
+       armv7m->swjdp_info.tar_autoincr_block = (1 << 12);
 
        /* register arch-specific functions */
        armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;