ADIv5: remove ATOMIC/COMPOSITE interface mode

[openocd] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 3dd9468594acf17844b69761a00a56f5aefd41be..3ebc34ad7fadb6ea6b9dccbfce5a6034c29eb384 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -70,8 +70,6 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
 
        mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 
-       swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
        /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
        dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
        dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
@@ -101,8 +99,6 @@ static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
 
        mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 
-       swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
        /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
        dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
        dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);