* any longer.
*/
+/**
+ * Returns the type of a break point required by address location
+ */
+#define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
+
/* forward declarations */
static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
static int cortex_m3_poll(struct target *target)
{
- int retval;
+ int detected_failure = ERROR_OK;
+ int retval = ERROR_OK;
enum target_state prev_target_state = target->state;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
/* Recover from lockup. See ARMv7-M architecture spec,
* section B1.5.15 "Unrecoverable exception cases".
- *
- * REVISIT Is there a better way to report and handle this?
*/
if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
- LOG_WARNING("%s -- clearing lockup after double fault",
+ LOG_ERROR("%s -- clearing lockup after double fault",
target_name(target));
cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
target->debug_reason = DBG_REASON_DBGRQ;
+ /* We have to execute the rest (the "finally" equivalent, but
+ * still throw this exception again).
+ */
+ detected_failure = ERROR_FAIL;
+
/* refresh status bits */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (retval != ERROR_OK)
if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
{
target->state = TARGET_RUNNING;
- return ERROR_OK;
+ retval = ERROR_OK;
}
}
- return ERROR_OK;
+ /* Did we detect a failure condition that we cleared? */
+ if (detected_failure != ERROR_OK)
+ retval = detected_failure;
+ return retval;
}
static int cortex_m3_halt(struct target *target)
if (!current)
buf_set_u32(pc->value, 0, 32, address);
+ uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
+
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints) {
- breakpoint = breakpoint_find(target,
- buf_get_u32(pc->value, 0, 32));
+ breakpoint = breakpoint_find(target, pc_value);
if (breakpoint)
cortex_m3_unset_breakpoint(target, breakpoint);
}
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
- int assert_srst = 1;
+ enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
LOG_DEBUG("target->state: %s",
target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
- /*
- * We can reset Cortex-M3 targets using just the NVIC without
- * requiring SRST, getting a SoC reset (or a core-only reset)
- * instead of a system reset.
- */
- if (!(jtag_reset_config & RESET_HAS_SRST))
- assert_srst = 0;
+ if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+ /* allow scripts to override the reset event */
+
+ target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+ register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ target->state = TARGET_RESET;
+
+ return ERROR_OK;
+ }
/* Enable debug requests */
int retval;
return retval;
}
- /*
- * When nRST is asserted on most Stellaris devices, it clears some of
- * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
- * and OpenOCD depends on those TRMs. So we won't use SRST on those
- * chips. (Only power-on reset should affect debug state, beyond a
- * few specified bits; not the chip's nRST input, wired to SRST.)
- *
- * REVISIT current errata specs don't seem to cover this issue.
- * Do we have more details than this email?
- * https://lists.berlios.de/pipermail
- * /openocd-development/2008-August/003065.html
- */
- if (strcmp(target->variant, "lm3s") == 0)
- {
- /* Check for silicon revisions with the issue. */
- uint32_t did0;
-
- if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
- {
- switch ((did0 >> 16) & 0xff)
- {
- case 0:
- /* all Sandstorm suffer issue */
- assert_srst = 0;
- break;
-
- case 1:
- case 3:
- /* Fury and DustDevil rev A have
- * this nRST problem. It should
- * be fixed in rev B silicon.
- */
- if (((did0 >> 8) & 0xff) == 0)
- assert_srst = 0;
- break;
- case 4:
- /* Tempest should be fine. */
- break;
- }
- }
- }
-
- if (assert_srst)
+ if (jtag_reset_config & RESET_HAS_SRST)
{
/* default to asserting srst */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
else
{
/* Use a standard Cortex-M3 software reset mechanism.
- * SYSRESETREQ will reset SoC peripherals outside the
- * core, like watchdog timers, if the SoC wires it up
- * correctly. Else VECRESET can reset just the core.
+ * We default to using VECRESET as it is supported on all current cores.
+ * This has the disadvantage of not resetting the peripherals, so a
+ * reset-init event handler is needed to perform any peripheral resets.
*/
retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
- AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
+ AIRCR_VECTKEY | ((reset_config == CORTEX_M3_RESET_SYSRESETREQ)
+ ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
+
+ LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
+ ? "SYSRESETREQ" : "VECTRESET");
+
+ if (reset_config == CORTEX_M3_RESET_VECTRESET) {
+ LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
+ "handler to reset any peripherals");
+ }
{
/* I do not know why this is necessary, but it
if (cortex_m3->auto_bp_type)
{
- breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
+ breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
}
if (breakpoint->type == BKPT_HARD)
if (cortex_m3->auto_bp_type)
{
- breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
+ breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
#ifdef ARMV7_GDB_HACKS
if (breakpoint->length != 2) {
/* XXX Hack: Replace all breakpoints with length != 2 with
#endif
}
- if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
- {
- LOG_INFO("flash patch comparator requested outside code memory region");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
+ if(breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
+ if (breakpoint->type == BKPT_HARD)
+ {
+ LOG_INFO("flash patch comparator requested outside code memory region");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
- if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
- {
- LOG_INFO("soft breakpoint requested in code (flash) memory region");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ if (breakpoint->type == BKPT_SOFT)
+ {
+ LOG_INFO("soft breakpoint requested in code (flash) memory region");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
}
if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
if (breakpoint->type == BKPT_HARD)
cortex_m3->fp_code_available--;
- cortex_m3_set_breakpoint(target, breakpoint);
- return ERROR_OK;
+ return cortex_m3_set_breakpoint(target, breakpoint);
}
static int
if (cortex_m3->auto_bp_type)
{
- breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
+ breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
}
if (breakpoint->set)
{
struct reg *r;
- LOG_ERROR("JTAG failure %i", retval);
+ LOG_ERROR("JTAG failure");
r = armv7m->core_cache->reg_list + num;
r->dirty = r->valid;
return ERROR_JTAG_DEVICE_ERROR;
}
static int cortex_m3_write_memory(struct target *target, uint32_t address,
- uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = &armv7m->dap;
}
static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
- uint32_t count, uint8_t *buffer)
+ uint32_t count, const uint8_t *buffer)
{
return cortex_m3_write_memory(target, address, 4, count, buffer);
}
cortex_m3->jtag_info.tap = tap;
cortex_m3->jtag_info.scann_size = 4;
+ /* default reset mode is to use srst if fitted
+ * if not it will use CORTEX_M3_RESET_VECTRESET */
+ cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
+
armv7m->arm.dap = &armv7m->dap;
/* Leave (only) generic DAP stuff for debugport_init(); */
return ERROR_OK;
}
+COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ int retval;
+ char *reset_config;
+
+ retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (CMD_ARGC > 0)
+ {
+ if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
+ cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
+ else if (strcmp(*CMD_ARGV, "vectreset") == 0)
+ cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
+ }
+
+ switch (cortex_m3->soft_reset_config)
+ {
+ case CORTEX_M3_RESET_SYSRESETREQ:
+ reset_config = "sysresetreq";
+ break;
+
+ case CORTEX_M3_RESET_VECTRESET:
+ reset_config = "vectreset";
+ break;
+
+ default:
+ reset_config = "unknown";
+ break;
+ }
+
+ command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
+
+ return ERROR_OK;
+}
+
static const struct command_registration cortex_m3_exec_command_handlers[] = {
{
.name = "maskisr",
.help = "configure hardware vectors to trigger debug entry",
.usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
},
+ {
+ .name = "reset_config",
+ .handler = handle_cortex_m3_reset_config_command,
+ .mode = COMMAND_ANY,
+ .help = "configure software reset handling",
+ .usage = "['srst'|'sysresetreq'|'vectreset']",
+ },
COMMAND_REGISTRATION_DONE
};
static const struct command_registration cortex_m3_command_handlers[] = {
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