- fixed ETM configuration register decoding

[openocd] / src / target / cortex_m3.h

diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index 63a5c43b19ce9357cd2e125ff1491c1dff0d3435..d51c4a490f5bf363a9a96c361fca3061c538e038 100644 (file)
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -40,7 +40,6 @@ extern char* cortex_m3_state_strings[];
 #define DCB_DCRDR      0xE000EDF8
 #define DCB_DEMCR      0xE000EDFC
 
-
 #define DCRSR_WnR      (1<<16) 
 
 #define DWT_CTRL       0xE0001000
@@ -107,7 +106,6 @@ extern char* cortex_m3_state_strings[];
 #define DFSR_DWTTRAP   4
 #define DFSR_VCATCH    8
 
-
 #define FPCR_CODE 0
 #define FPCR_LITERAL 1
 #define FPCR_REPLACE_REMAP  (0<<30)
@@ -149,16 +147,16 @@ typedef struct cortex_m3_common_s
        int fp_num_code;
        int fp_code_available;
        int auto_bp_type;
-       cortex_m3_fp_comparator_t * fp_comparator_list;
+       cortex_m3_fp_comparator_t *fp_comparator_list;
        
        /* DWT */
        int dwt_num_comp;
        int dwt_comp_available;
-       cortex_m3_dwt_comparator_t * dwt_comparator_list;
+       cortex_m3_dwt_comparator_t *dwt_comparator_list;
        
        /* Interrupts */
        int intlinesnum;
-       u32 * intsetenable;
+       u32 *intsetenable;
        
 /*
        u32 arm_bkpt;
@@ -189,7 +187,6 @@ typedef struct cortex_m3_common_s
        void *arch_info;
 } cortex_m3_common_t;
 
-
 extern void cortex_m3_build_reg_cache(target_t *target);
 
 enum target_state cortex_m3_poll(target_t *target);
@@ -200,6 +197,7 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle
 int cortex_m3_assert_reset(target_t *target);
 int cortex_m3_deassert_reset(target_t *target);
 int cortex_m3_soft_reset_halt(struct target_s *target);
+int cortex_m3_prepare_reset_halt(struct target_s *target);
 
 int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);