arm920t line length cleanup

[openocd] / src / target / embeddedice.c

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index eb04bd12ed74c4d307212eaf1d213c2fc43e1294..bf220364e653a33630a426e243b8faefeb8747f6 100644 (file)
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -35,7 +35,8 @@
  *
  * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT)
  * module found on scan chain 2 in ARM7, ARM9, and some other families
- * of ARM cores.
+ * of ARM cores.  The module is called "EmbeddedICE-RT" if it has
+ * monitor mode support.
  *
  * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug
  * Communications Channel (DCC) used to read or write 32-bit words to
@@ -191,6 +192,11 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
        reg_cache->reg_list = reg_list;
        reg_cache->num_regs = num_regs;
 
+       /* FIXME the second watchpoint unit on Feroceon and Dragonite
+        * seems not to work ... we should have a way to not set up
+        * its four registers here!
+        */
+
        /* set up registers */
        for (i = 0; i < num_regs; i++)
        {
@@ -289,8 +295,10 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
                                buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
        }
 
-       LOG_INFO("%s: hardware has 2 breakpoints or watchpoints",
-                       target_name(target));
+       /* On Feroceon and Dragonite the second unit is seemingly missing. */
+       LOG_INFO("%s: hardware has %d breakpoint/watchpoint unit%s",
+                       target_name(target), arm7_9->wp_available_max,
+                       (arm7_9->wp_available_max != 1) ? "s" : "");
 
        return reg_cache;
 }