ARM ADIv5: rename more JTAG-specific routines

[openocd] / src / target / etb.c

diff --git a/src/target/etb.c b/src/target/etb.c
index 3113eca0651c70750436b71cb2a255b86586b511..18258f6acc793238f4574963978943d04a8d000e 100644 (file)
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -402,12 +402,67 @@ COMMAND_HANDLER(handle_etb_config_command)
        return ERROR_OK;
 }
 
+COMMAND_HANDLER(handle_etb_trigger_percent_command)
+{
+       struct target *target;
+       struct arm *arm;
+       struct etm_context *etm;
+       struct etb *etb;
+
+       target = get_current_target(CMD_CTX);
+       arm = target_to_arm(target);
+       if (!is_arm(arm))
+       {
+               command_print(CMD_CTX, "ETB: current target isn't an ARM");
+               return ERROR_FAIL;
+       }
+
+       etm = arm->etm;
+       if (!etm) {
+               command_print(CMD_CTX, "ETB: target has no ETM configured");
+               return ERROR_FAIL;
+       }
+       if (etm->capture_driver != &etb_capture_driver) {
+               command_print(CMD_CTX, "ETB: target not using ETB");
+               return ERROR_FAIL;
+       }
+       etb = arm->etm->capture_driver_priv;
+
+       if (CMD_ARGC > 0) {
+               uint32_t new_value;
+
+               COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
+               if ((new_value < 2) || (new_value > 100))
+                       command_print(CMD_CTX,
+                               "valid percentages are 2%% to 100%%");
+               else
+                       etb->trigger_percent = (unsigned) new_value;
+       }
+
+       command_print(CMD_CTX, "%d percent of tracebuffer fills after trigger",
+                       etb->trigger_percent);
+
+       return ERROR_OK;
+}
+
 static const struct command_registration etb_config_command_handlers[] = {
        {
+               /* NOTE:  with ADIv5, ETBs are accessed using DAP operations,
+                * possibly over SWD, not through separate TAPs...
+                */
                .name = "config",
-               .handler = &handle_etb_config_command,
+               .handler = handle_etb_config_command,
                .mode = COMMAND_CONFIG,
-               .usage = "<target> <tap>",
+               .help = "Associate ETB with target and JTAG TAP.",
+               .usage = "target tap",
+       },
+       {
+               .name = "trigger_percent",
+               .handler = handle_etb_trigger_percent_command,
+               .mode = COMMAND_EXEC,
+               .help = "Set percent of trace buffer to be filled "
+                       "after the trigger occurs (2..100).",
+               .usage = "[percent]",
        },
        COMMAND_REGISTRATION_DONE
 };
@@ -435,6 +490,8 @@ static int etb_init(struct etm_context *etm_ctx)
        etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
        etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
 
+       etb->trigger_percent = 50;
+
        return ERROR_OK;
 }
 
@@ -526,9 +583,9 @@ static int etb_read_trace(struct etm_context *etm_ctx)
                free(etm_ctx->trace_data);
        }
 
-       if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
+       if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
                etm_ctx->trace_depth = num_frames * 3;
-       else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
+       else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
                etm_ctx->trace_depth = num_frames * 2;
        else
                etm_ctx->trace_depth = num_frames;
@@ -537,7 +594,7 @@ static int etb_read_trace(struct etm_context *etm_ctx)
 
        for (i = 0, j = 0; i < num_frames; i++)
        {
-               if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
+               if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
                {
                        /* trace word j */
                        etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
@@ -583,7 +640,7 @@ static int etb_read_trace(struct etm_context *etm_ctx)
 
                        j += 3;
                }
-               else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
+               else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
                {
                        /* trace word j */
                        etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
@@ -646,9 +703,9 @@ static int etb_start_capture(struct etm_context *etm_ctx)
        uint32_t etb_ctrl_value = 0x1;
        uint32_t trigger_count;
 
-       if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
+       if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
        {
-               if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
+               if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
                {
                        LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
                        return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
@@ -656,12 +713,12 @@ static int etb_start_capture(struct etm_context *etm_ctx)
                etb_ctrl_value |= 0x2;
        }
 
-       if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
+       if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
                LOG_ERROR("ETB: can't run in multiplexed mode");
                return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
        }
 
-       trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
+       trigger_count = (etb->ram_depth * etb->trigger_percent) / 100;
 
        etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
        etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);