#include <stdlib.h>
-char* etb_reg_list[] =
+static char* etb_reg_list[] =
{
"ETB_identification",
"ETB_ram_depth",
"ETB_control",
};
-int etb_reg_arch_type = -1;
+static int etb_reg_arch_type = -1;
-int etb_get_reg(reg_t *reg);
-int etb_set_reg(reg_t *reg, u32 value);
-int etb_set_reg_w_exec(reg_t *reg, u8 *buf);
+static int etb_get_reg(reg_t *reg);
-int etb_write_reg(reg_t *reg, u32 value);
-int etb_read_reg(reg_t *reg);
+static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-
-int etb_set_instr(etb_t *etb, u32 new_instr)
+static int etb_set_instr(etb_t *etb, u32 new_instr)
{
- jtag_device_t *device = jtag_get_device(etb->chain_pos);
- if (device==NULL)
+ jtag_tap_t *tap;
+
+ tap = etb->tap;
+ if (tap==NULL)
return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
- field.device = etb->chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
- field.out_mask = NULL;
+
field.in_value = NULL;
- field.in_check_value = NULL;
- field.in_check_mask = NULL;
- field.in_handler = NULL;
- field.in_handler_priv = NULL;
- jtag_add_ir_scan(1, &field, -1);
+ jtag_add_ir_scan(1, &field, TAP_INVALID);
free(field.out_value);
}
return ERROR_OK;
}
-int etb_scann(etb_t *etb, u32 new_scan_chain)
+static int etb_scann(etb_t *etb, u32 new_scan_chain)
{
- if(etb->cur_scan_chain != new_scan_chain)
+ if (etb->cur_scan_chain != new_scan_chain)
{
scan_field_t field;
- field.device = etb->chain_pos;
+ field.tap = etb->tap;
field.num_bits = 5;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
- field.out_mask = NULL;
+
field.in_value = NULL;
- field.in_check_value = NULL;
- field.in_check_mask = NULL;
- field.in_handler = NULL;
- field.in_handler_priv = NULL;
/* select INTEST instruction */
etb_set_instr(etb, 0x2);
- jtag_add_dr_scan(1, &field, -1);
+ jtag_add_dr_scan(1, &field, TAP_INVALID);
etb->cur_scan_chain = new_scan_chain;
return reg_cache;
}
-int etb_get_reg(reg_t *reg)
+static int etb_get_reg(reg_t *reg)
{
int retval;
+
if ((retval = etb_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register read");
return ERROR_OK;
}
-int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
+static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
{
scan_field_t fields[3];
int i;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
etb_scann(etb, 0x0);
etb_set_instr(etb, 0xc);
- fields[0].device = etb->chain_pos;
+ fields[0].tap = etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
- fields[0].out_mask = NULL;
- fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
+ u8 tmp[4];
+ fields[0].in_value = tmp;
- fields[1].device = etb->chain_pos;
+ fields[1].tap = etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, 4);
- fields[1].out_mask = NULL;
fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- fields[2].device = etb->chain_pos;
+ fields[2].tap = etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
- fields[2].out_mask = NULL;
fields[2].in_value = NULL;
- fields[2].in_check_value = NULL;
- fields[2].in_check_mask = NULL;
- fields[2].in_handler = NULL;
- fields[2].in_handler_priv = NULL;
-
- jtag_add_dr_scan(3, fields, -1);
- fields[0].in_handler = buf_to_u32_handler;
+ jtag_add_dr_scan(3, fields, TAP_INVALID);
for (i = 0; i < num_frames; i++)
{
else
buf_set_u32(fields[1].out_value, 0, 7, 0);
- fields[0].in_handler_priv = &data[i];
- jtag_add_dr_scan(3, fields, -1);
+ jtag_add_dr_scan_now(3, fields, TAP_INVALID);
+
+ data[i]=buf_get_u32(tmp, 0, 32);
}
jtag_execute_queue();
LOG_DEBUG("%i", etb_reg->addr);
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
- fields[0].device = etb_reg->etb->chain_pos;
+ fields[0].tap = etb_reg->etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
- fields[0].out_mask = NULL;
fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
- fields[1].device = etb_reg->etb->chain_pos;
+ fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
- fields[1].out_mask = NULL;
fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- fields[2].device = etb_reg->etb->chain_pos;
+ fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
- fields[2].out_mask = NULL;
fields[2].in_value = NULL;
- fields[2].in_check_value = NULL;
- fields[2].in_check_mask = NULL;
- fields[2].in_handler = NULL;
- fields[2].in_handler_priv = NULL;
- jtag_add_dr_scan(3, fields, -1);
+ jtag_add_dr_scan(3, fields, TAP_INVALID);
/* read the identification register in the second run, to make sure we
* don't read the ETB data register twice, skipping every second entry
buf_set_u32(fields[1].out_value, 0, 7, 0x0);
fields[0].in_value = reg->value;
- jtag_set_check_value(fields+0, check_value, check_mask, NULL);
+ jtag_add_dr_scan(3, fields, TAP_INVALID);
- jtag_add_dr_scan(3, fields, -1);
+ jtag_check_value_mask(fields+0, check_value, check_mask);
free(fields[1].out_value);
free(fields[2].out_value);
int etb_set_reg(reg_t *reg, u32 value)
{
int retval;
+
if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register write");
int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int retval;
+
etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
if ((retval = jtag_execute_queue()) != ERROR_OK)
LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
- fields[0].device = etb_reg->etb->chain_pos;
+ fields[0].tap = etb_reg->etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = malloc(4);
buf_set_u32(fields[0].out_value, 0, 32, value);
- fields[0].out_mask = NULL;
fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
- fields[1].device = etb_reg->etb->chain_pos;
+ fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
- fields[1].out_mask = NULL;
fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- fields[2].device = etb_reg->etb->chain_pos;
+ fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 1);
- fields[2].out_mask = NULL;
- fields[2].in_value = NULL;
- fields[2].in_check_value = NULL;
- fields[2].in_check_mask = NULL;
- fields[2].in_handler = NULL;
- fields[2].in_handler_priv = NULL;
- jtag_add_dr_scan(3, fields, -1);
+ fields[2].in_value = NULL;
free(fields[0].out_value);
free(fields[1].out_value);
return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
}
-int etb_register_commands(struct command_context_s *cmd_ctx)
+static int etb_register_commands(struct command_context_s *cmd_ctx)
{
command_t *etb_cmd;
return ERROR_OK;
}
-int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target;
- jtag_device_t *jtag_device;
+ jtag_tap_t *tap;
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
return ERROR_FAIL;
}
- jtag_device = jtag_get_device(strtoul(args[1], NULL, 0));
-
- if (!jtag_device)
+ tap = jtag_TapByString( args[1] );
+ if (tap == NULL)
{
+ command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
return ERROR_FAIL;
}
arm7_9->etm_ctx->capture_driver_priv = etb;
- etb->chain_pos = strtoul(args[1], NULL, 0);
- etb->cur_scan_chain = -1;
+ etb->tap = tap;
+ etb->cur_scan_chain = 0xffffffff;
etb->reg_cache = NULL;
etb->ram_width = 0;
etb->ram_depth = 0;
return ERROR_OK;
}
-int etb_init(etm_context_t *etm_ctx)
+static int etb_init(etm_context_t *etm_ctx)
{
etb_t *etb = etm_ctx->capture_driver_priv;
return ERROR_OK;
}
-trace_status_t etb_status(etm_context_t *etm_ctx)
+static trace_status_t etb_status(etm_context_t *etm_ctx)
{
etb_t *etb = etm_ctx->capture_driver_priv;
return etm_ctx->capture_status;
}
-int etb_read_trace(etm_context_t *etm_ctx)
+static int etb_read_trace(etm_context_t *etm_ctx)
{
etb_t *etb = etm_ctx->capture_driver_priv;
int first_frame = 0;
return ERROR_OK;
}
-int etb_start_capture(etm_context_t *etm_ctx)
+static int etb_start_capture(etm_context_t *etm_ctx)
{
etb_t *etb = etm_ctx->capture_driver_priv;
u32 etb_ctrl_value = 0x1;
return ERROR_OK;
}
-int etb_stop_capture(etm_context_t *etm_ctx)
+static int etb_stop_capture(etm_context_t *etm_ctx)
{
etb_t *etb = etm_ctx->capture_driver_priv;
reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
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