]> git.sur5r.net Git - openocd/blobdiff - src/target/etm.h
- fixed ETM configuration register decoding
[openocd] / src / target / etm.h
index 65fd757c8d3971b117f11150d7250162d5cfefcd..bfa1252b761ca4284da449754785a326c1d0b73e 100644 (file)
@@ -103,7 +103,8 @@ typedef enum
        ETMV1_CONTEXTID_32   = 0x30,\r
        ETMV1_CONTEXTID_MASK = 0x30,\r
        /* Misc */\r
-       ETMV1_CYCLE_ACCURATE = 0x100\r
+       ETMV1_CYCLE_ACCURATE = 0x100,\r
+       ETMV1_BRANCH_OUTPUT = 0x200\r
 } etmv1_tracemode_t;\r
 \r
 /* forward-declare ETM context */\r
@@ -120,11 +121,17 @@ typedef struct etm_capture_driver_s
        int (*stop_capture)(struct etm_context_s *etm_ctx);\r
 } etm_capture_driver_t;\r
 \r
+enum\r
+{\r
+       ETMV1_TRACESYNC_CYCLE = 0x1,\r
+       ETMV1_TRIGGER_CYCLE = 0x2,\r
+};\r
+\r
 typedef struct etmv1_trace_data_s\r
 {\r
-       u8 pipestat;    /* pipeline cycle this packet belongs to */\r
-       u16 packet;     /* packet data (4, 8 or 16 bit) */\r
-       int tracesync;  /* 1 if tracesync was set on this packet */\r
+       u8 pipestat;    /* bits 0-2 pipeline status */\r
+       u16 packet;             /* packet data (4, 8 or 16 bit) */\r
+       int flags;              /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */\r
 } etmv1_trace_data_t;\r
 \r
 /* describe a trace context\r
@@ -134,23 +141,29 @@ typedef struct etmv1_trace_data_s
  */\r
 typedef struct etm_context_s\r
 {\r
+       target_t *target;                               /* target this ETM is connected to */\r
        reg_cache_t *reg_cache;                 /* ETM register cache */\r
        etm_capture_driver_t *capture_driver;   /* driver used to access ETM data */\r
        void *capture_driver_priv;              /* capture driver private data */\r
+       u32 trigger_percent;                    /* percent of trace buffer to be filled after the trigger */\r
        trace_status_t capture_status;  /* current state of capture run */ \r
        etmv1_trace_data_t *trace_data; /* trace data */\r
        u32 trace_depth;                                /* number of trace cycles to be analyzed, 0 if no trace data available */\r
        etm_portmode_t portmode;                /* normal, multiplexed or demultiplexed */\r
        etmv1_tracemode_t tracemode;    /* type of information the trace contains (data, addres, contextID, ...) */ \r
        armv4_5_state_t core_state;             /* current core state (ARM, Thumb, Jazelle) */\r
-       image_t image;                                  /* source for target opcodes */\r
+       image_t *image;                                 /* source for target opcodes */\r
        u32 pipe_index;                                 /* current trace cycle */\r
        u32 data_index;                                 /* cycle holding next data packet */\r
+       int data_half;                                  /* port half on a 16 bit port */\r
        u32 current_pc;                                 /* current program counter */\r
        u32 pc_ok;                                              /* full PC has been acquired */\r
        u32 last_branch;                                /* last branch address output */ \r
+       u32 last_branch_reason;                 /* branch reason code for the last branch encountered */\r
        u32 last_ptr;                                   /* address of the last data access */\r
+       u32 ptr_ok;                                             /* whether last_ptr is valid */ \r
        u32 context_id;                                 /* context ID of the code being traced */\r
+       u32 last_instruction;                   /* index of last instruction executed (to calculate cycle timings) */\r
 } etm_context_t;\r
 \r
 /* PIPESTAT values */\r
@@ -196,5 +209,6 @@ extern etm_context_t* etm_create_context(etm_portmode_t portmode, char *capture_
 #define ERROR_ETM_INVALID_DRIVER       (-1300)\r
 #define ERROR_ETM_PORTMODE_NOT_SUPPORTED       (-1301)\r
 #define ERROR_ETM_CAPTURE_INIT_FAILED  (-1302)\r
+#define ERROR_ETM_ANALYSIS_FAILED      (-1303)\r
 \r
 #endif /* ETM_H */\r