#include "arm926ejs.h"
#include "arm966e.h"
#include "target_type.h"
+#include "register.h"
+#include "arm_opcodes.h"
-int feroceon_assert_reset(target_t *target)
+
+int feroceon_assert_reset(struct target *target)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
fields[0].in_value = NULL;
- fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf;
fields[1].in_value = NULL;
- fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = instr_buf;
fields[2].in_value = NULL;
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
/* no jtag_add_runtest(0, jtag_get_end_state()) here */
return ERROR_OK;
}
-void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
+void feroceon_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
*pc -= (12 + 4);
}
-void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
+void feroceon_read_core_regs(struct target *target, uint32_t mask, uint32_t* core_regs[16])
{
int i;
struct arm *armv4_5 = target->arch_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
+void feroceon_read_core_regs_target_buffer(struct target *target, uint32_t mask, void* buffer, int size)
{
int i;
struct arm *armv4_5 = target->arch_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
+void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
+void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
+void feroceon_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, int spsr)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
+void feroceon_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16])
{
int i;
struct arm *armv4_5 = target->arch_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void feroceon_branch_resume(target_t *target)
+void feroceon_branch_resume(struct target *target)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm7_9->need_bypass_before_restart = 1;
}
-void feroceon_branch_resume_thumb(target_t *target)
+void feroceon_branch_resume_thumb(struct target *target)
{
LOG_DEBUG("-");
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
- uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ uint32_t pc = buf_get_u32(armv4_5->pc->value, 0, 32);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm7_9->need_bypass_before_restart = 1;
}
-int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+int feroceon_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
return jtag_execute_queue();
}
-int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+int feroceon_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
return arm7_9_execute_sys_speed(target);
}
-void feroceon_set_dbgrq(target_t *target)
+void feroceon_set_dbgrq(struct target *target)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+ struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
buf_set_u32(dbg_ctrl->value, 0, 8, 2);
embeddedice_store_reg(dbg_ctrl);
}
-void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
+void feroceon_enable_single_step(struct target *target, uint32_t next_pc)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
}
-void feroceon_disable_single_step(target_t *target)
+void feroceon_disable_single_step(struct target *target)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
}
-int feroceon_examine_debug_reason(target_t *target)
+int feroceon_examine_debug_reason(struct target *target)
{
/* the MOE is not implemented */
if (target->debug_reason != DBG_REASON_SINGLESTEP)
return ERROR_OK;
}
-int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
+int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- enum armv4_5_state core_state = armv4_5->core_state;
+ enum arm_state core_state = armv4_5->core_state;
uint32_t x, flip, shift, save[7];
uint32_t i;
/* backup clobbered processor state */
for (i = 0; i <= 5; i++)
save[i] = buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32);
- save[i] = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ save[i] = buf_get_u32(armv4_5->pc->value, 0, 32);
/* set up target address in r0 */
buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
armv4_5->core_cache->reg_list[0].valid = 1;
armv4_5->core_cache->reg_list[0].dirty = 1;
- armv4_5->core_state = ARMV4_5_STATE_ARM;
+ armv4_5->core_state = ARM_STATE_ARM;
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
armv4_5->core_cache->reg_list[i].valid = 1;
armv4_5->core_cache->reg_list[i].dirty = 1;
}
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, save[i]);
- armv4_5->core_cache->reg_list[15].valid = 1;
- armv4_5->core_cache->reg_list[15].dirty = 1;
+ buf_set_u32(armv4_5->pc->value, 0, 32, save[i]);
+ armv4_5->pc->valid = 1;
+ armv4_5->pc->dirty = 1;
armv4_5->core_state = core_state;
return retval;
}
-int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+int feroceon_init_target(struct command_context *cmd_ctx, struct target *target)
{
arm9tdmi_init_target(cmd_ctx, target);
return ERROR_OK;
}
-void feroceon_common_setup(struct target_s *target)
+void feroceon_common_setup(struct target *target)
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm7_9->wp1_used_default = -1;
}
-int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
+int feroceon_target_create(struct target *target, Jim_Interp *interp)
{
struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
return ERROR_OK;
}
-int dragonite_target_create(struct target_s *target, Jim_Interp *interp)
+int dragonite_target_create(struct target *target, Jim_Interp *interp)
{
struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common));
return ERROR_OK;
}
-int feroceon_examine(struct target_s *target)
+int feroceon_examine(struct target *target)
{
struct arm *armv4_5;
struct arm7_9_common *arm7_9;
int retval;
- retval = arm9tdmi_examine(target);
+ retval = arm7_9_examine(target);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
-target_type_t feroceon_target =
+struct target_type feroceon_target =
{
.name = "feroceon",
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm926ejs_soft_reset_halt,
- .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+ .get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.write_memory = arm926ejs_write_memory,
.bulk_write_memory = feroceon_bulk_write_memory,
- .checksum_memory = arm7_9_checksum_memory,
- .blank_check_memory = arm7_9_blank_check_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm,
.add_watchpoint = arm7_9_add_watchpoint,
.remove_watchpoint = arm7_9_remove_watchpoint,
- .register_commands = arm926ejs_register_commands,
+ .commands = arm926ejs_command_handlers,
.target_create = feroceon_target_create,
.init_target = feroceon_init_target,
.examine = feroceon_examine,
};
-target_type_t dragonite_target =
+struct target_type dragonite_target =
{
.name = "dragonite",
.poll = arm7_9_poll,
- .arch_state = armv4_5_arch_state,
+ .arch_state = arm_arch_state,
.target_request_data = arm7_9_target_request_data,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
- .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+ .get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.write_memory = arm7_9_write_memory,
.bulk_write_memory = feroceon_bulk_write_memory,
- .checksum_memory = arm7_9_checksum_memory,
- .blank_check_memory = arm7_9_blank_check_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm,
.add_watchpoint = arm7_9_add_watchpoint,
.remove_watchpoint = arm7_9_remove_watchpoint,
- .register_commands = arm966e_register_commands,
+ .commands = arm966e_command_handlers,
.target_create = dragonite_target_create,
.init_target = feroceon_init_target,
.examine = feroceon_examine,