armv4_5_common_t -> struct arm

[openocd] / src / target / feroceon.c

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 3026ed22c108bdb442e5eed9e2d25d4785cfb2a7..cf034c428963a9011f3e077e9a41d5629a1d66a6 100644 (file)
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -58,7 +58,7 @@
 
 int feroceon_assert_reset(target_t *target)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        int ud = arm7_9->use_dbgrq;
 
@@ -69,7 +69,7 @@ int feroceon_assert_reset(target_t *target)
        return arm7_9_assert_reset(target);
 }
 
-int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr)
+int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 {
        struct scan_field fields[3];
        uint8_t out_buf[4];
@@ -110,9 +110,9 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr)
 
 void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
        /*
         * save r0 before using it and put system in ARM state
@@ -157,9 +157,9 @@ void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
 void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
 {
        int i;
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
        arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -176,9 +176,9 @@ void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_reg
 void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
 {
        int i;
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       struct arm_jtag *jtag_info = &arm7_9->jtag_info;
        int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
        uint32_t *buf_u32 = buffer;
        uint16_t *buf_u16 = buffer;
@@ -212,9 +212,9 @@ void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void
 
 void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
        arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -235,9 +235,9 @@ void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
 
 void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
        LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
 
@@ -276,9 +276,9 @@ void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
 
 void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
        LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 
@@ -294,9 +294,9 @@ void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int sps
 void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
 {
        int i;
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
        arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -313,9 +313,9 @@ void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg
 
 void feroceon_branch_resume(target_t *target)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -330,9 +330,9 @@ void feroceon_branch_resume_thumb(target_t *target)
 {
        LOG_DEBUG("-");
 
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       struct arm_jtag *jtag_info = &arm7_9->jtag_info;
        uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
        uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
 
@@ -363,9 +363,9 @@ void feroceon_branch_resume_thumb(target_t *target)
 
 int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       struct arm_jtag *jtag_info = &arm7_9->jtag_info;
        int err;
 
        arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
@@ -385,9 +385,9 @@ int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CR
 
 int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
        arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -404,7 +404,7 @@ int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t C
 
 void feroceon_set_dbgrq(target_t *target)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
@@ -414,7 +414,7 @@ void feroceon_set_dbgrq(target_t *target)
 
 void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 
        /* set a breakpoint there */
@@ -427,7 +427,7 @@ void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
 
 void feroceon_disable_single_step(target_t *target)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 
        embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
@@ -451,7 +451,7 @@ int feroceon_examine_debug_reason(target_t *target)
 int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
        int retval;
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        enum armv4_5_state core_state = armv4_5->core_state;
        uint32_t x, flip, shift, save[7];
@@ -585,7 +585,7 @@ int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *tar
 
 void feroceon_common_setup(struct target_s *target)
 {
-       armv4_5_common_t *armv4_5 = target->arch_info;
+       struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 
        /* override some insn sequence functions */
@@ -632,7 +632,7 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
 
 int dragonite_target_create(struct target_s *target, Jim_Interp *interp)
 {
-       arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));
+       struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common));
 
        arm966e_init_arch_info(target, arm966e, target->tap);
        feroceon_common_setup(target);
@@ -642,7 +642,7 @@ int dragonite_target_create(struct target_s *target, Jim_Interp *interp)
 
 int feroceon_examine(struct target_s *target)
 {
-       armv4_5_common_t *armv4_5;
+       struct arm *armv4_5;
        struct arm7_9_common *arm7_9;
        int retval;