ARM ADIv5: rename more JTAG-specific routines

[openocd] / src / target / feroceon.c

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 432d49d1b08d6fb4e6a484fa4e2bc1684672e3f3..e0c3c3954480f3dc6118ae9d54f50c2561bd8db4 100644 (file)
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -56,6 +56,7 @@
 #include "arm966e.h"
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 int feroceon_assert_reset(struct target *target)
@@ -336,7 +337,7 @@ void feroceon_branch_resume_thumb(struct target *target)
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
        uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
-       uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+       uint32_t pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -455,7 +456,7 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
        int retval;
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       enum armv4_5_state core_state = armv4_5->core_state;
+       enum arm_state core_state = armv4_5->core_state;
        uint32_t x, flip, shift, save[7];
        uint32_t i;
 
@@ -518,13 +519,13 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
        /* backup clobbered processor state */
        for (i = 0; i <= 5; i++)
                save[i] = buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32);
-       save[i] = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+       save[i] = buf_get_u32(armv4_5->pc->value, 0, 32);
 
        /* set up target address in r0 */
        buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
        armv4_5->core_cache->reg_list[0].valid = 1;
        armv4_5->core_cache->reg_list[0].dirty = 1;
-       armv4_5->core_state = ARMV4_5_STATE_ARM;
+       armv4_5->core_state = ARM_STATE_ARM;
 
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
        arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
@@ -571,9 +572,9 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
                armv4_5->core_cache->reg_list[i].valid = 1;
                armv4_5->core_cache->reg_list[i].dirty = 1;
        }
-       buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, save[i]);
-       armv4_5->core_cache->reg_list[15].valid = 1;
-       armv4_5->core_cache->reg_list[15].dirty = 1;
+       buf_set_u32(armv4_5->pc->value, 0, 32, save[i]);
+       armv4_5->pc->valid = 1;
+       armv4_5->pc->dirty = 1;
        armv4_5->core_state = core_state;
 
        return retval;
@@ -693,7 +694,7 @@ struct target_type feroceon_target =
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm926ejs_soft_reset_halt,
 
-       .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+       .get_gdb_reg_list = arm_get_gdb_reg_list,
 
        .read_memory = arm7_9_read_memory,
        .write_memory = arm926ejs_write_memory,
@@ -720,7 +721,7 @@ struct target_type dragonite_target =
        .name = "dragonite",
 
        .poll = arm7_9_poll,
-       .arch_state = armv4_5_arch_state,
+       .arch_state = arm_arch_state,
 
        .target_request_data = arm7_9_target_request_data,
 
@@ -732,7 +733,7 @@ struct target_type dragonite_target =
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm7_9_soft_reset_halt,
 
-       .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+       .get_gdb_reg_list = arm_get_gdb_reg_list,
 
        .read_memory = arm7_9_read_memory,
        .write_memory = arm7_9_write_memory,