]> git.sur5r.net Git - openocd/blobdiff - src/target/hla_target.c
armv7m: use generic arm::core_mode
[openocd] / src / target / hla_target.c
index 8d2a4291a634e81047e56ccbd7c7ee732a49c661..11926c78dd138291b10c093ead5bb9168d0cb426 100644 (file)
@@ -339,25 +339,23 @@ static int adapter_debug_entry(struct target *target)
        adapter_load_context(target);
 
        /* make sure we clear the vector catch bit */
-       adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, 0);
+       adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
 
        r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
        xPSR = buf_get_u32(r->value, 0, 32);
 
        /* Are we in an exception handler */
        if (xPSR & 0x1FF) {
-               armv7m->core_mode = ARMV7M_MODE_HANDLER;
                armv7m->exception_number = (xPSR & 0x1FF);
 
                arm->core_mode = ARM_MODE_HANDLER;
                arm->map = armv7m_msp_reg_map;
        } else {
-               unsigned control = buf_get_u32(armv7m->core_cache
+               unsigned control = buf_get_u32(arm->core_cache
                                ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 
                /* is this thread privileged? */
-               armv7m->core_mode = control & 1;
-               arm->core_mode = armv7m->core_mode
+               arm->core_mode = control & 1
                                ? ARM_MODE_USER_THREAD
                                : ARM_MODE_THREAD;
 
@@ -371,7 +369,7 @@ static int adapter_debug_entry(struct target *target)
        }
 
        LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
-               armv7m_mode_strings[armv7m->core_mode],
+               arm_mode_name(arm->core_mode),
                *(uint32_t *)(arm->pc->value),
                target_state_name(target));
 
@@ -434,9 +432,9 @@ static int adapter_assert_reset(struct target *target)
 
        /* only set vector catch if halt is requested */
        if (target->reset_halt)
-               adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, VC_CORERESET);
+               adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA|VC_CORERESET);
        else
-               adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, 0);
+               adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
 
        if (jtag_reset_config & RESET_HAS_SRST) {
                if (!srst_asserted) {
@@ -571,6 +569,11 @@ static int adapter_resume(struct target *target, int current,
 
        resume_pc = buf_get_u32(pc->value, 0, 32);
 
+       /* write any user vector flags */
+       res = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
+       if (res != ERROR_OK)
+               return res;
+
        armv7m_restore_context(target);
 
        /* registers are now invalid */