Revert "cortex_m3: add auto maskisr"

[openocd] / src / target / mips32.c

diff --git a/src/target/mips32.c b/src/target/mips32.c
index b0cb79ccd5ab16ef47c50f4058c14a83210714e1..65ea6e859193058e863d979f9bc9ddc3366d5590 100644 (file)
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -31,7 +31,7 @@
 #include "algorithm.h"
 #include "register.h"
 
-char* mips32_core_reg_list[] =
+static char* mips32_core_reg_list[] =
 {
        "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
        "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
@@ -40,12 +40,12 @@ char* mips32_core_reg_list[] =
        "status", "lo", "hi", "badvaddr", "cause", "pc"
 };
 
-const char *mips_isa_strings[] =
+static const char *mips_isa_strings[] =
 {
        "MIPS32", "MIPS16e"
 };
 
-struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
+static struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
 {
        {0, NULL, NULL},
        {1, NULL, NULL},
@@ -93,9 +93,9 @@ struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
 
 #define MIPS32NUMFPREGS 34 + 18
 
-uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
+static uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
 
-struct reg mips32_gdb_dummy_fp_reg =
+static struct reg mips32_gdb_dummy_fp_reg =
 {
        .name = "GDB dummy floating-point register",
        .value = mips32_gdb_dummy_fp_value,
@@ -105,7 +105,7 @@ struct reg mips32_gdb_dummy_fp_reg =
        .arch_info = NULL,
 };
 
-int mips32_get_core_reg(struct reg *reg)
+static int mips32_get_core_reg(struct reg *reg)
 {
        int retval;
        struct mips32_core_reg *mips32_reg = reg->arch_info;
@@ -122,7 +122,7 @@ int mips32_get_core_reg(struct reg *reg)
        return retval;
 }
 
-int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
+static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
 {
        struct mips32_core_reg *mips32_reg = reg->arch_info;
        struct target *target = mips32_reg->target;
@@ -140,10 +140,9 @@ int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
        return ERROR_OK;
 }
 
-int mips32_read_core_reg(struct target *target, int num)
+static int mips32_read_core_reg(struct target *target, int num)
 {
        uint32_t reg_value;
-       struct mips32_core_reg *mips_core_reg;
 
        /* get pointers to arch-specific information */
        struct mips32_common *mips32 = target_to_mips32(target);
@@ -151,7 +150,6 @@ int mips32_read_core_reg(struct target *target, int num)
        if ((num < 0) || (num >= MIPS32NUMCOREREGS))
                return ERROR_INVALID_ARGUMENTS;
 
-       mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
        reg_value = mips32->core_regs[num];
        buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
        mips32->core_cache->reg_list[num].valid = 1;
@@ -160,10 +158,9 @@ int mips32_read_core_reg(struct target *target, int num)
        return ERROR_OK;
 }
 
-int mips32_write_core_reg(struct target *target, int num)
+static int mips32_write_core_reg(struct target *target, int num)
 {
        uint32_t reg_value;
-       struct mips32_core_reg *mips_core_reg;
 
        /* get pointers to arch-specific information */
        struct mips32_common *mips32 = target_to_mips32(target);
@@ -172,7 +169,6 @@ int mips32_write_core_reg(struct target *target, int num)
                return ERROR_INVALID_ARGUMENTS;
 
        reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
-       mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
        mips32->core_regs[num] = reg_value;
        LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
        mips32->core_cache->reg_list[num].valid = 1;
@@ -309,6 +305,7 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s
 {
        target->arch_info = mips32;
        mips32->common_magic = MIPS32_COMMON_MAGIC;
+       mips32->fast_data_area = NULL;
 
        /* has breakpoint/watchpint unit been scanned */
        mips32->bp_scanned = 0;
@@ -348,9 +345,9 @@ static int mips32_run_and_wait(struct target *target, uint32_t entry_point,
        }
 
        pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
-       if (pc != exit_point)
+       if (exit_point && (pc != exit_point))
        {
-               LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
+               LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
                return ERROR_TARGET_TIMEOUT;
        }
 
@@ -388,7 +385,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
        }
 
        /* refresh core register cache */
-       for (unsigned i = 0; i < MIPS32NUMCOREREGS; i++)
+       for (i = 0; i < MIPS32NUMCOREREGS; i++)
        {
                if (!mips32->core_cache->reg_list[i].valid)
                        mips32->read_core_reg(target, i);
@@ -404,7 +401,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
                }
        }
 
-       for (int i = 0; i < num_reg_params; i++)
+       for (i = 0; i < num_reg_params; i++)
        {
                struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
 
@@ -558,6 +555,13 @@ int mips32_configure_break_unit(struct target *target)
                        return retval;
        }
 
+       /* check if target endianness settings matches debug control register */
+       if ( (  (dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN) ) ||
+               ( !(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN)    ) )
+       {
+               LOG_WARNING("DCR endianness settings does not match target settings");
+       }
+
        LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
                        mips32->num_data_bpoints);
 
@@ -613,6 +617,8 @@ int mips32_checksum_memory(struct target *target, uint32_t address,
        int retval;
        uint32_t i;
 
+       /* see contib/loaders/checksum/mips32.s for src */
+
        static const uint32_t mips_crc_code[] =
        {
                0x248C0000,             /* addiu        $t4, $a0, 0 */
@@ -662,8 +668,10 @@ int mips32_checksum_memory(struct target *target, uint32_t address,
        init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
        buf_set_u32(reg_params[1].value, 0, 32, count);
 
+       int timeout = 20000 * (1 + (count / (1024 * 1024)));
+
        if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
-                       crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), 10000,
+                       crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), timeout,
                        &mips32_info)) != ERROR_OK)
        {
                destroy_reg_param(&reg_params[0]);