int num_regs = MIPS32NUMCOREREGS;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
- struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
+ struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
int i;
if (retval != ERROR_OK)
return retval;
- /* EJTAG 2.0 does not specify EJTAG_DCR_IB and EJTAG_DCR_DB bits,
- * assume IB and DB registers are always present. */
- if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
- dcr |= EJTAG_DCR_IB | EJTAG_DCR_DB;
+ /* EJTAG 2.0 defines IB and DB bits in IMP instead of DCR. */
+ if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
+ ejtag_info->debug_caps = dcr & EJTAG_DCR_ENM;
+ if (!(ejtag_info->impcode & EJTAG_V20_IMP_NOIB))
+ ejtag_info->debug_caps |= EJTAG_DCR_IB;
+ if (!(ejtag_info->impcode & EJTAG_V20_IMP_NODB))
+ ejtag_info->debug_caps |= EJTAG_DCR_DB;
+ } else
+ /* keep debug caps for later use */
+ ejtag_info->debug_caps = dcr & (EJTAG_DCR_ENM
+ | EJTAG_DCR_IB | EJTAG_DCR_DB);
- if (dcr & EJTAG_DCR_IB) {
+
+ if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
retval = mips32_configure_ibs(target);
if (retval != ERROR_OK)
return retval;
}
- if (dcr & EJTAG_DCR_DB) {
+ if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
retval = mips32_configure_dbs(target);
if (retval != ERROR_OK)
return retval;
}
/* check if target endianness settings matches debug control register */
- if (((dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN)) ||
- (!(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN)))
+ if (((ejtag_info->debug_caps & EJTAG_DCR_ENM)
+ && (target->endianness == TARGET_LITTLE_ENDIAN)) ||
+ (!(ejtag_info->debug_caps & EJTAG_DCR_ENM)
+ && (target->endianness == TARGET_BIG_ENDIAN)))
LOG_WARNING("DCR endianness settings does not match target settings");
LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
struct working_area *crc_algorithm;
struct reg_param reg_params[2];
struct mips32_algorithm mips32_info;
- int retval;
- uint32_t i;
- /* see contib/loaders/checksum/mips32.s for src */
+ /* see contrib/loaders/checksum/mips32.s for src */
static const uint32_t mips_crc_code[] = {
0x248C0000, /* addiu $t4, $a0, 0 */
if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- /* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++)
- target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), mips_crc_code[i]);
+ /* convert mips crc code into a buffer in target endianness */
+ uint8_t mips_crc_code_8[sizeof(mips_crc_code)];
+ target_buffer_set_u32_array(target, mips_crc_code_8,
+ ARRAY_SIZE(mips_crc_code), mips_crc_code);
+
+ target_write_buffer(target, crc_algorithm->address, sizeof(mips_crc_code), mips_crc_code_8);
mips32_info.common_magic = MIPS32_COMMON_MAGIC;
mips32_info.isa_mode = MIPS32_ISA_MIPS32;
int timeout = 20000 * (1 + (count / (1024 * 1024)));
- retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
- crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), timeout,
+ int retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
+ crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code) - 4), timeout,
&mips32_info);
- if (retval != ERROR_OK) {
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- target_free_working_area(target, crc_algorithm);
- return retval;
- }
- *checksum = buf_get_u32(reg_params[0].value, 0, 32);
+ if (retval == ERROR_OK)
+ *checksum = buf_get_u32(reg_params[0].value, 0, 32);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
target_free_working_area(target, crc_algorithm);
- return ERROR_OK;
+ return retval;
}
/** Checks whether a memory region is zeroed. */
struct working_area *erase_check_algorithm;
struct reg_param reg_params[3];
struct mips32_algorithm mips32_info;
- int retval;
- uint32_t i;
static const uint32_t erase_check_code[] = {
/* nbyte: */
if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- /* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < ARRAY_SIZE(erase_check_code); i++) {
- target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t),
- erase_check_code[i]);
- }
+ /* convert erase check code into a buffer in target endianness */
+ uint8_t erase_check_code_8[sizeof(erase_check_code)];
+ target_buffer_set_u32_array(target, erase_check_code_8,
+ ARRAY_SIZE(erase_check_code), erase_check_code);
+
+ target_write_buffer(target, erase_check_algorithm->address, sizeof(erase_check_code), erase_check_code_8);
mips32_info.common_magic = MIPS32_COMMON_MAGIC;
mips32_info.isa_mode = MIPS32_ISA_MIPS32;
init_reg_param(®_params[2], "a2", 32, PARAM_IN_OUT);
buf_set_u32(reg_params[2].value, 0, 32, 0xff);
- retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
+ int retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
erase_check_algorithm->address,
- erase_check_algorithm->address + (sizeof(erase_check_code)-4),
+ erase_check_algorithm->address + (sizeof(erase_check_code) - 4),
10000, &mips32_info);
- if (retval != ERROR_OK) {
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- destroy_reg_param(®_params[2]);
- target_free_working_area(target, erase_check_algorithm);
- return retval;
- }
- *blank = buf_get_u32(reg_params[2].value, 0, 32);
+ if (retval == ERROR_OK)
+ *blank = buf_get_u32(reg_params[2].value, 0, 32);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
target_free_working_area(target, erase_check_algorithm);
- return ERROR_OK;
+ return retval;
}
static int mips32_verify_pointer(struct command_context *cmd_ctx,
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