whitespace fixes

[openocd] / src / target / mips32.h

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 72035b4c16b8440d4aa42c258df8dc634ace0409..049ce8f50e73afec1bff4484ec887582b2e9168d 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -74,6 +74,7 @@ typedef struct mips32_core_reg_s
 } mips32_core_reg_t;
 
 #define MIPS32_OP_BEQ  0x04
+#define MIPS32_OP_BNE  0x05
 #define MIPS32_OP_ADDI 0x08
 #define MIPS32_OP_AND  0x24
 #define MIPS32_OP_COP0 0x10
@@ -93,7 +94,7 @@ typedef struct mips32_core_reg_s
 #define MIPS32_COP0_MF 0x00
 #define MIPS32_COP0_MT 0x04
 
-#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)        (((opcode)<<26) |((rs)<<21)|((rt)<<16)|((rd)<<11)| ((shamt)<<5) | (funct))
+#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)        (((opcode)<<26) |((rs)<<21)|((rt)<<16)|((rd)<<11)| ((shamt)<<6) | (funct))
 #define MIPS32_I_INST(opcode, rs, rt, immd)    (((opcode)<<26) |((rs)<<21)|((rt)<<16)|(immd))
 #define MIPS32_J_INST(opcode, addr)    (((opcode)<<26) |(addr))
 
@@ -102,6 +103,7 @@ typedef struct mips32_core_reg_s
 #define MIPS32_AND(reg, off, val)      MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
 #define MIPS32_B(off)                          MIPS32_BEQ(0, 0, off)
 #define MIPS32_BEQ(src,tar,off)                MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
+#define MIPS32_BNE(src,tar,off)                MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
 #define MIPS32_MFC0(gpr, cpr, sel)     MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
 #define MIPS32_MTC0(gpr,cpr, sel)      MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
 #define MIPS32_LBU(reg, off, base)     MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
@@ -110,8 +112,8 @@ typedef struct mips32_core_reg_s
 #define MIPS32_LW(reg, off, base)      MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
 #define MIPS32_MFLO(reg)                       MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
 #define MIPS32_MFHI(reg)                       MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
-#define MIPS32_MTLO(reg)                       MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTLO)
-#define MIPS32_MTHI(reg)                       MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTHI)
+#define MIPS32_MTLO(reg)                       MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
+#define MIPS32_MTHI(reg)                       MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
 #define MIPS32_ORI(src, tar, val)      MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
 #define MIPS32_SB(reg, off, base)      MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
 #define MIPS32_SH(reg, off, base)      MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)