mips32: add gdb target description support

[openocd] / src / target / mips32.h

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 0bdfc59607189f903ac0b7a96b7221fc7c672246..56f4fb4e1b9a231e253c35e290d13c0aa1b0293c 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -20,7 +20,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifndef MIPS32_H
@@ -66,6 +66,7 @@
 /* offsets into mips32 core register cache */
 enum {
        MIPS32_PC = 37,
+       MIPS32_FIR = 71,
        MIPS32NUMCOREREGS
 };
 
@@ -100,8 +101,8 @@ struct mips32_common {
        struct mips32_comparator *data_break_list;
 
        /* register cache to processor synchronization */
-       int (*read_core_reg)(struct target *target, int num);
-       int (*write_core_reg)(struct target *target, int num);
+       int (*read_core_reg)(struct target *target, unsigned int num);
+       int (*write_core_reg)(struct target *target, unsigned int num);
 };
 
 static inline struct mips32_common *
@@ -130,6 +131,7 @@ struct mips32_algorithm {
 #define MIPS32_OP_AND  0x24
 #define MIPS32_OP_CACHE        0x2F
 #define MIPS32_OP_COP0 0x10
+#define MIPS32_OP_J    0x02
 #define MIPS32_OP_JR   0x08
 #define MIPS32_OP_LUI  0x0F
 #define MIPS32_OP_LW   0x23
@@ -175,6 +177,7 @@ struct mips32_algorithm {
 #define MIPS32_BGTZ(reg, off)                  MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)
 #define MIPS32_BNE(src, tar, off)              MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
 #define MIPS32_CACHE(op, off, base)            MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)
+#define MIPS32_J(tar)                          MIPS32_J_INST(MIPS32_OP_J, tar)
 #define MIPS32_JR(reg)                                 MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
 #define MIPS32_MFC0(gpr, cpr, sel)             MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
 #define MIPS32_MTC0(gpr, cpr, sel)             MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
@@ -201,7 +204,7 @@ struct mips32_algorithm {
 #define MIPS32_SYNCI_STEP      0x1     /* reg num od address step size to be used with synci instruction */
 
 /**
- * Cache operations definietions
+ * Cache operations definitions
  * Operation field is 5 bits long :
  * 1) bits 1..0 hold cache type
  * 2) bits 4..2 hold operation code
@@ -241,7 +244,8 @@ int mips32_examine(struct target *target);
 int mips32_register_commands(struct command_context *cmd_ctx);
 
 int mips32_get_gdb_reg_list(struct target *target,
-               struct reg **reg_list[], int *reg_list_size);
+               struct reg **reg_list[], int *reg_list_size,
+               enum target_register_class reg_class);
 int mips32_checksum_memory(struct target *target, uint32_t address,
                uint32_t count, uint32_t *checksum);
 int mips32_blank_check_memory(struct target *target,