mips32: add gdb target description support

[openocd] / src / target / mips32.h

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 97fb5d03729d1b1d4ec709b10f234cfae1bbe7a6..56f4fb4e1b9a231e253c35e290d13c0aa1b0293c 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -66,6 +66,7 @@
 /* offsets into mips32 core register cache */
 enum {
        MIPS32_PC = 37,
+       MIPS32_FIR = 71,
        MIPS32NUMCOREREGS
 };
 
@@ -100,8 +101,8 @@ struct mips32_common {
        struct mips32_comparator *data_break_list;
 
        /* register cache to processor synchronization */
-       int (*read_core_reg)(struct target *target, int num);
-       int (*write_core_reg)(struct target *target, int num);
+       int (*read_core_reg)(struct target *target, unsigned int num);
+       int (*write_core_reg)(struct target *target, unsigned int num);
 };
 
 static inline struct mips32_common *
@@ -203,7 +204,7 @@ struct mips32_algorithm {
 #define MIPS32_SYNCI_STEP      0x1     /* reg num od address step size to be used with synci instruction */
 
 /**
- * Cache operations definietions
+ * Cache operations definitions
  * Operation field is 5 bits long :
  * 1) bits 1..0 hold cache type
  * 2) bits 4..2 hold operation code
@@ -243,7 +244,8 @@ int mips32_examine(struct target *target);
 int mips32_register_commands(struct command_context *cmd_ctx);
 
 int mips32_get_gdb_reg_list(struct target *target,
-               struct reg **reg_list[], int *reg_list_size);
+               struct reg **reg_list[], int *reg_list_size,
+               enum target_register_class reg_class);
 int mips32_checksum_memory(struct target *target, uint32_t address,
                uint32_t count, uint32_t *checksum);
 int mips32_blank_check_memory(struct target *target,