mips32: use 'unsigned int' for CPU register indices

[openocd] / src / target / mips32.h

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 5d5aa465047b5174797ab7f7342aa70bd8da340e..bfd7facb1dd59d3326a2fa3f45441a6ba26abee6 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -20,7 +20,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifndef MIPS32_H
@@ -64,27 +64,23 @@
 #define MIPS32_ARCH_REL2 0x1
 
 /* offsets into mips32 core register cache */
-enum
-{
+enum {
        MIPS32_PC = 37,
        MIPS32NUMCOREREGS
 };
 
-enum mips32_isa_mode
-{
+enum mips32_isa_mode {
        MIPS32_ISA_MIPS32 = 0,
        MIPS32_ISA_MIPS16E = 1,
 };
 
-struct mips32_comparator
-{
+struct mips32_comparator {
        int used;
        uint32_t bp_value;
        uint32_t reg_address;
 };
 
-struct mips32_common
-{
+struct mips32_common {
        uint32_t common_magic;
        void *arch_info;
        struct reg_cache *core_cache;
@@ -104,8 +100,8 @@ struct mips32_common
        struct mips32_comparator *data_break_list;
 
        /* register cache to processor synchronization */
-       int (*read_core_reg)(struct target *target, int num);
-       int (*write_core_reg)(struct target *target, int num);
+       int (*read_core_reg)(struct target *target, unsigned int num);
+       int (*write_core_reg)(struct target *target, unsigned int num);
 };
 
 static inline struct mips32_common *
@@ -114,15 +110,13 @@ target_to_mips32(struct target *target)
        return target->arch_info;
 }
 
-struct mips32_core_reg
-{
+struct mips32_core_reg {
        uint32_t num;
        struct target *target;
        struct mips32_common *mips32_common;
 };
 
-struct mips32_algorithm
-{
+struct mips32_algorithm {
        int common_magic;
        enum mips32_isa_mode isa_mode;
 };
@@ -136,6 +130,7 @@ struct mips32_algorithm
 #define MIPS32_OP_AND  0x24
 #define MIPS32_OP_CACHE        0x2F
 #define MIPS32_OP_COP0 0x10
+#define MIPS32_OP_J    0x02
 #define MIPS32_OP_JR   0x08
 #define MIPS32_OP_LUI  0x0F
 #define MIPS32_OP_LW   0x23
@@ -150,6 +145,7 @@ struct mips32_algorithm
 #define MIPS32_OP_SH   0x29
 #define MIPS32_OP_SW   0x2B
 #define MIPS32_OP_ORI  0x0D
+#define MIPS32_OP_XORI 0x0E
 #define MIPS32_OP_XOR  0x26
 #define MIPS32_OP_SLTU  0x2B
 #define MIPS32_OP_SRL  0x03
@@ -164,9 +160,11 @@ struct mips32_algorithm
 #define MIPS32_COP0_MF 0x00
 #define MIPS32_COP0_MT 0x04
 
-#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)        (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct))
-#define MIPS32_I_INST(opcode, rs, rt, immd)    (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd))
-#define MIPS32_J_INST(opcode, addr)    (((opcode) << 26) |(addr))
+#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) \
+       (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct))
+#define MIPS32_I_INST(opcode, rs, rt, immd) \
+       (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | (immd))
+#define MIPS32_J_INST(opcode, addr)    (((opcode) << 26) | (addr))
 
 #define MIPS32_NOP                                             0
 #define MIPS32_ADDI(tar, src, val)             MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
@@ -176,8 +174,9 @@ struct mips32_algorithm
 #define MIPS32_B(off)                                  MIPS32_BEQ(0, 0, off)
 #define MIPS32_BEQ(src, tar, off)              MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
 #define MIPS32_BGTZ(reg, off)                  MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)
-#define MIPS32_BNE(src,tar,off)                        MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
+#define MIPS32_BNE(src, tar, off)              MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
 #define MIPS32_CACHE(op, off, base)            MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)
+#define MIPS32_J(tar)                          MIPS32_J_INST(MIPS32_OP_J, tar)
 #define MIPS32_JR(reg)                                 MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
 #define MIPS32_MFC0(gpr, cpr, sel)             MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
 #define MIPS32_MTC0(gpr, cpr, sel)             MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
@@ -190,6 +189,7 @@ struct mips32_algorithm
 #define MIPS32_MTLO(reg)                               MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
 #define MIPS32_MTHI(reg)                               MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
 #define MIPS32_ORI(tar, src, val)              MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
+#define MIPS32_XORI(tar, src, val)             MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val)
 #define MIPS32_RDHWR(tar, dst)                 MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)
 #define MIPS32_SB(reg, off, base)              MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
 #define MIPS32_SH(reg, off, base)              MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
@@ -203,7 +203,7 @@ struct mips32_algorithm
 #define MIPS32_SYNCI_STEP      0x1     /* reg num od address step size to be used with synci instruction */
 
 /**
- * Cache operations definietions
+ * Cache operations definitions
  * Operation field is 5 bits long :
  * 1) bits 1..0 hold cache type
  * 2) bits 4..2 hold operation code
@@ -243,10 +243,11 @@ int mips32_examine(struct target *target);
 int mips32_register_commands(struct command_context *cmd_ctx);
 
 int mips32_get_gdb_reg_list(struct target *target,
-               struct reg **reg_list[], int *reg_list_size);
+               struct reg **reg_list[], int *reg_list_size,
+               enum target_register_class reg_class);
 int mips32_checksum_memory(struct target *target, uint32_t address,
-               uint32_t count, uint32_t* checksum);
+               uint32_t count, uint32_t *checksum);
 int mips32_blank_check_memory(struct target *target,
-               uint32_t address, uint32_t count, uint32_t* blank);
+               uint32_t address, uint32_t count, uint32_t *blank);
 
 #endif /*MIPS32_H*/