struct mips32_comparator *data_break_list;
/* register cache to processor synchronization */
- int (*read_core_reg)(struct target *target, int num);
- int (*write_core_reg)(struct target *target, int num);
+ int (*read_core_reg)(struct target *target, unsigned int num);
+ int (*write_core_reg)(struct target *target, unsigned int num);
};
static inline struct mips32_common *
#define MIPS32_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */
/**
- * Cache operations definietions
+ * Cache operations definitions
* Operation field is 5 bits long :
* 1) bits 1..0 hold cache type
* 2) bits 4..2 hold operation code