* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "mips32.h"
#include "mips_ejtag.h"
+#include "mips32_dmaacc.h"
void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
{
return ERROR_OK;
}
+void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
+{
+ assert(ejtag_info->tap != NULL);
+ struct jtag_tap *tap = ejtag_info->tap;
+
+ struct scan_field field;
+ uint8_t out_scan[12];
+
+ /* processor access "all" register 96 bit */
+ field.num_bits = 96;
+
+ field.out_value = out_scan;
+ buf_set_u32(out_scan, 0, 32, ctrl);
+ buf_set_u32(out_scan + 4, 0, 32, data);
+ buf_set_u32(out_scan + 8, 0, 32, 0);
+
+ field.in_value = in_scan_buf;
+
+ jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
+
+ keep_alive();
+}
+
int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
{
struct jtag_tap *tap;
/* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
{
- int code_len = enable_step ? 6 : 7;
-
- uint32_t *code = malloc(code_len * sizeof(uint32_t));
- if (code == NULL) {
- LOG_ERROR("Out of memory");
- return ERROR_FAIL;
- }
- uint32_t *code_p = code;
+ struct pracc_queue_info ctx = {.max_code = 7};
+ pracc_queue_init(&ctx);
+ if (ctx.retval != ERROR_OK)
+ goto exit;
- *code_p++ = MIPS32_MTC0(1, 31, 0); /* move $1 to COP0 DeSave */
- *code_p++ = MIPS32_MFC0(1, 23, 0), /* move COP0 Debug to $1 */
- *code_p++ = MIPS32_ORI(1, 1, 0x0100); /* set SSt bit in debug reg */
+ pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0)); /* move COP0 Debug to $8 */
+ pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100)); /* set SSt bit in debug reg */
if (!enable_step)
- *code_p++ = MIPS32_XORI(1, 1, 0x0100); /* clear SSt bit in debug reg */
+ pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100)); /* clear SSt bit in debug reg */
- *code_p++ = MIPS32_MTC0(1, 23, 0); /* move $1 to COP0 Debug */
- *code_p++ = MIPS32_B(NEG16((code_len - 1))); /* jump to start */
- *code_p = MIPS32_MFC0(1, 31, 0); /* move COP0 DeSave to $1 */
+ pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0)); /* move $8 to COP0 Debug */
+ pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1)))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
- int retval = mips32_pracc_exec(ejtag_info, code_len, code, 0, NULL, 0, NULL, 1);
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
+exit:
+ pracc_queue_free(&ctx);
+ return ctx.retval;
+}
+
+/*
+ * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
+ * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
+ * For example bcm7401 and others. At leas on some
+ * CPUs, DebugMode wont start if this bit is not removed.
+ */
+static int disable_dcr_mp(struct mips_ejtag *ejtag_info)
+{
+ uint32_t dcr;
+ int retval;
- free(code);
+ retval = mips32_dmaacc_read_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
+ if (retval != ERROR_OK)
+ goto error;
+
+ dcr &= ~EJTAG_DCR_MP;
+ retval = mips32_dmaacc_write_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
+ if (retval != ERROR_OK)
+ goto error;
+ return ERROR_OK;
+error:
+ LOG_ERROR("Failed to remove DCR MPbit!");
return retval;
}
uint32_t ejtag_ctrl;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
+ if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
+ if (disable_dcr_mp(ejtag_info) != ERROR_OK)
+ goto error;
+ }
+
/* set debug break bit */
ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
- if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) {
- LOG_ERROR("Failed to enter Debug Mode!");
- return ERROR_FAIL;
- }
+ if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
+ goto error;
return ERROR_OK;
+error:
+ LOG_ERROR("Failed to enter Debug Mode!");
+ return ERROR_FAIL;
}
int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
{
- uint32_t inst;
- inst = MIPS32_DRET;
+ uint32_t instr = MIPS32_DRET;
+ struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &instr, .code_count = 1, .store_count = 0};
/* execute our dret instruction */
- int retval = mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
/* pic32mx workaround, false pending at low core clock */
jtag_add_sleep(1000);
-
- return retval;
+ return ctx.retval;
}
int mips_ejtag_init(struct mips_ejtag *ejtag_info)
{
- uint32_t ejtag_version;
int retval;
retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
/* get ejtag version */
- ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
+ ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
- switch (ejtag_version) {
- case 0:
+ switch (ejtag_info->ejtag_version) {
+ case EJTAG_VERSION_20:
LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
break;
- case 1:
+ case EJTAG_VERSION_25:
LOG_DEBUG("EJTAG: Version 2.5 Detected");
break;
- case 2:
+ case EJTAG_VERSION_26:
LOG_DEBUG("EJTAG: Version 2.6 Detected");
break;
- case 3:
+ case EJTAG_VERSION_31:
LOG_DEBUG("EJTAG: Version 3.1 Detected");
break;
- case 4:
+ case EJTAG_VERSION_41:
LOG_DEBUG("EJTAG: Version 4.1 Detected");
break;
- case 5:
+ case EJTAG_VERSION_51:
LOG_DEBUG("EJTAG: Version 5.1 Detected");
break;
default:
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