uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
/* read ejtag control reg */
- jtag_set_end_state(TAP_IDLE);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
/* clear this bit before handling polling
{
/* we have detected a reset, clear flag
* otherwise ejtag will not work */
- jtag_set_end_state(TAP_IDLE);
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("Reset Detected");
}
{
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
- jtag_set_end_state(TAP_IDLE);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
target->state = TARGET_HALTED;
if (target->reset_halt)
{
/* use hardware to catch reset */
- jtag_set_end_state(TAP_IDLE);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
}
else
{
- jtag_set_end_state(TAP_IDLE);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
}
if (assert_srst)
}
else
{
+ if (mips_m4k->is_pic32mx)
+ {
+ uint32_t mchip_cmd;
+
+ LOG_DEBUG("Using MTAP reset to reset processor...");
+
+ /* use microchip specific MTAP reset */
+ mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
+ mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
+
+ mchip_cmd = MCHP_ASERT_RST;
+ mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+ mchip_cmd = MCHP_DE_ASSERT_RST;
+ mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+ mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
+ }
+ else
+ {
/* use ejtag reset - not supported by all cores */
uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ }
}
target->state = TARGET_RESET;
int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k,
struct jtag_tap *tap)
{
- struct mips32_common *mips32 = &mips_m4k->mips32_common;
+ struct mips32_common *mips32 = &mips_m4k->mips32;
mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
int mips_m4k_examine(struct target *target)
{
int retval;
- struct mips32_common *mips32 = target_to_mips32(target);
- struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+ struct mips_m4k_common *mips_m4k = target_to_m4k(target);
+ struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
uint32_t idcode = 0;
if (!target_was_examined(target))
{
/* we are using a pic32mx so select ejtag port
* as it is not selected by default */
- mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL);
+ mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
+ mips_m4k->is_pic32mx = true;
}
}