#include "mips32.h"
#include "mips_m4k.h"
#include "mips32_dmaacc.h"
-#include "jtag.h"
-#include "log.h"
-#include <stdlib.h>
-#include <string.h>
/* cli handling */
int mips_m4k_examine(struct target_s *target);
int mips_m4k_assert_reset(target_t *target);
int mips_m4k_deassert_reset(target_t *target);
+int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum);
target_type_t mips_m4k_target =
{
.read_memory = mips_m4k_read_memory,
.write_memory = mips_m4k_write_memory,
.bulk_write_memory = mips_m4k_bulk_write_memory,
- .checksum_memory = NULL,
+ .checksum_memory = mips_m4k_checksum_memory,
.blank_check_memory = NULL,
.run_algorithm = mips32_run_algorithm,
int mips_m4k_examine_debug_reason(target_t *target)
{
- int break_status;
+ u32 break_status;
int retval;
if ((target->debug_reason != DBG_REASON_DBGRQ)
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
- mips_m4k_common_t *mips_m4k = mips32->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
}
- if (strcmp(mips_m4k->variant, "ejtag_srst") == 0)
+ if (strcmp(target->variant, "ejtag_srst") == 0)
{
u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
/* configure single step mode */
mips_ejtag_config_step(ejtag_info, 1);
+ /* disable interrupts while stepping */
+ mips32_enable_interrupts(target, 0);
+
/* exit debug mode */
- mips_ejtag_exit_debug(ejtag_info, 1);
+ mips_ejtag_exit_debug(ejtag_info);
mips_m4k_debug_entry(target);
}
}
- /* exit debug mode - enable interrupts if required */
- mips_ejtag_exit_debug(ejtag_info, !debug_execution);
+ /* enable interrupts if we are running */
+ mips32_enable_interrupts(target, !debug_execution);
+
+ /* exit debug mode */
+ mips_ejtag_exit_debug(ejtag_info);
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+ /* disable interrupts while stepping */
+ mips32_enable_interrupts(target, 0);
+
/* exit debug mode */
- mips_ejtag_exit_debug(ejtag_info, 1);
+ mips_ejtag_exit_debug(ejtag_info);
/* registers are now invalid */
mips32_invalidate_core_regs(target);
{
mips32_common_t *mips32 = target->arch_info;
mips32_comparator_t * comparator_list = mips32->inst_break_list;
-
+ int retval;
+
if (breakpoint->set)
{
LOG_WARNING("breakpoint already set");
}
else if (breakpoint->type == BKPT_SOFT)
{
-
+ if (breakpoint->length == 4)
+ {
+ u32 verify = 0xffffffff;
+
+ if((retval = target->type->read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if (verify != MIPS32_SDBBP)
+ {
+ LOG_ERROR("Unable to set 32bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+ return ERROR_OK;
+ }
+ }
+ else
+ {
+ u16 verify = 0xffff;
+
+ if((retval = target->type->read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if (verify != MIPS16_SDBBP)
+ {
+ LOG_ERROR("Unable to set 16bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+ return ERROR_OK;
+ }
+ }
+
+ breakpoint->set = 20; /* Any nice value but 0 */
}
return ERROR_OK;
/* get pointers to arch-specific information */
mips32_common_t *mips32 = target->arch_info;
mips32_comparator_t * comparator_list = mips32->inst_break_list;
-
+ int retval;
+
if (!breakpoint->set)
{
LOG_WARNING("breakpoint not set");
}
else
{
-
+ /* restore original instruction (kept in target endianness) */
+ if (breakpoint->length == 4)
+ {
+ u32 current_instr;
+
+ /* check that user program has not modified breakpoint instruction */
+ if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if (current_instr == MIPS32_SDBBP)
+ {
+ if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ }
+ }
+ else
+ {
+ u16 current_instr;
+
+ /* check that user program has not modified breakpoint instruction */
+ if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if (current_instr == MIPS16_SDBBP)
+ {
+ if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ }
+ }
}
breakpoint->set = 0;
{
mips32_common_t *mips32 = target->arch_info;
- if (mips32->num_inst_bpoints_avail < 1)
+ if (breakpoint->type == BKPT_HARD)
{
- LOG_INFO("no hardware breakpoint available");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
-
- /* default to hardware for now */
- breakpoint->type = BKPT_HARD;
+ if (mips32->num_inst_bpoints_avail < 1)
+ {
+ LOG_INFO("no hardware breakpoint available");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ mips32->num_inst_bpoints_avail--;
+ }
- mips32->num_inst_bpoints_avail--;
mips_m4k_set_breakpoint(target, breakpoint);
return ERROR_OK;
return ERROR_OK;
}
-int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant)
+int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
{
mips32_common_t *mips32 = &mips_m4k->mips32_common;
- if (variant)
- {
- mips_m4k->variant = strdup(variant);
- }
- else
- {
- mips_m4k->variant = strdup("");
- }
-
mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
/* initialize mips4k specific info */
- mips32_init_arch_info(target, mips32, tap, variant);
+ mips32_init_arch_info(target, mips32, tap);
mips32->arch_info = mips_m4k;
return ERROR_OK;
{
mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
- mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant);
+ mips_m4k_init_arch_info(target, mips_m4k, target->tap);
return ERROR_OK;
}
if (!target->type->examined)
{
mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
-
+ ejtag_info->idcode = idcode;
+
if (((idcode >> 1) & 0x7FF) == 0x29)
{
/* we are using a pic32mx so select ejtag port
{
return mips_m4k_write_memory(target, address, 4, count, buffer);
}
+
+int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum)
+{
+ return ERROR_FAIL; /* use bulk read method */
+}
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