Rick Altherr <kc8apf@kc8apf.net> switch to new syntax for target events

[openocd] / src / target / target / eir-sam7se512.cfg

diff --git a/src/target/target/eir-sam7se512.cfg b/src/target/target/eir-sam7se512.cfg
index dfc247552e61824e4222035fbb3a8154b1f5afaf..bf53be1f349f9dfa13ccd31066b0a20219040ab4 100644 (file)
--- a/src/target/target/eir-sam7se512.cfg
+++ b/src/target/target/eir-sam7se512.cfg
@@ -8,7 +8,94 @@ jtag_device 4 0x1 0xf 0xe
 target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
 
 
-[new_target_name] configure -event reset-init { script event/eir-sam7se512_reset.script }
+[new_target_name] configure -event reset-init {
+       # WDT_MR, disable watchdog 
+       mww 0xFFFFFD44 0x00008000
+
+       # RSTC_MR, enable user reset
+       mww 0xfffffd08 0xa5000001
+
+       # CKGR_MOR
+       mww 0xFFFFFC20 0x00000601
+       sleep 10
+
+       # CKGR_PLLR
+       mww 0xFFFFFC2C 0x00481c0e
+       sleep 10
+
+       # PMC_MCKR
+       mww 0xFFFFFC30 0x00000007
+       sleep 10
+
+       # PMC_IER
+       mww 0xFFFFFF60 0x00480100
+
+       #
+       # Enable SDRAM interface.
+       #
+
+       # Enable SDRAM control at PIO A.
+       mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
+       mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
+
+       # Enable address bus (A0, A2-A11, A13-A17) at PIO B
+       mww 0xfffff674 0x0003effd # PIO_BSR_OFF
+       mww 0xfffff604 0x0003effd # PIO_PDR_OFF
+
+       # Enable 16 bit data bus at PIO C
+       mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
+       mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
+
+       # Enable SDRAM chip select
+       mww 0xffffff80 0x00000002 # EBI_CSA_OFF
+
+       # Set SDRAM characteristics in configuration register.
+       # Hard coded values for MT48LC32M16A2 with 48MHz CPU.
+       mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
+       sleep 10
+
+       # Issue 16 bit SDRAM command: NOP
+       mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
+       mww 0x20000000 0x00000000 
+
+       # Issue 16 bit SDRAM command: Precharge all
+       mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
+       mww 0x20000000 0x00000000 
+
+       # Issue 8 auto-refresh cycles
+       mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+       mww 0x20000000 0x00000000 
+       mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+       mww 0x20000000 0x00000000 
+       mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+       mww 0x20000000 0x00000000 
+       mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+       mww 0x20000000 0x00000000 
+       mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+       mww 0x20000000 0x00000000 
+       mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+       mww 0x20000000 0x00000000 
+       mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+       mww 0x20000000 0x00000000 
+       mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+       mww 0x20000000 0x00000000 
+
+       # Issue 16 bit SDRAM command: Set mode register  
+       mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
+       mww 0x20000014 0xcafedede
+
+       # Set refresh rate count ???
+       mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
+
+       # Issue 16 bit SDRAM command: Normal mode
+       mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
+       mww 0x20000000 0x00000180
+
+       #
+       # Enable external reset key.
+       #
+       mww 0xfffffd08 0xa5000001
+}
 
 [new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0