whitespace fixes

[openocd] / src / target / target / lm3s3748.cfg

diff --git a/src/target/target/lm3s3748.cfg b/src/target/target/lm3s3748.cfg
index 924c78a9499f8d141ef969a798597bc4c2d41f93..7321cb8ac7679dfe557656a9f8bf3174ebce7a02 100644 (file)
--- a/src/target/target/lm3s3748.cfg
+++ b/src/target/target/lm3s3748.cfg
@@ -1,28 +1,49 @@
-# Script for luminary lm3s3748\r
-#\r
-# NB! work in progress! Duplicated from lm3s811.cfg, but does\r
-# it need modification??\r
-\r
-# RCLK \r
-jtag_khz 500\r
-\r
-jtag_nsrst_delay 100\r
-jtag_ntrst_delay 100\r
-\r
-#lm3s3748 Evaluation Board has only srst\r
-reset_config srst_only\r
-\r
-#jtag scan chain\r
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
-jtag_device 4 0x1 0xf 0xe\r
-\r
-# the luminary variant causes a software reset rather than asserting SRST\r
-# this stops the debug registers from being cleared\r
-# this will be fixed in later revisions of silicon\r
-target cortex_m3 little 0 lm3s\r
-\r
-# 8k working area at base of ram\r
-working_area 0 0x20000000 0x2000 nobackup\r
-\r
-#flash configuration\r
-flash bank stellaris 0 0 0 0 0\r
+# Script for luminary lm3s3748
+#
+# NB! work in progress! Duplicated from lm3s811.cfg, but does
+# it need modification??
+
+if { [info exists CHIPNAME] } {        
+   set  _CHIPNAME $CHIPNAME    
+} else {        
+   set  _CHIPNAME lm3s3748
+}
+
+if { [info exists ENDIAN] } {  
+   set  _ENDIAN $ENDIAN    
+} else {        
+  # this defaults to a little endian
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x3ba00477
+}
+
+# RCLK 
+jtag_khz 500
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#lm3s3748 Evaluation Board has only srst
+reset_config srst_only
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+# the luminary variant causes a software reset rather than asserting SRST
+# this stops the debug registers from being cleared
+# this will be fixed in later revisions of silicon
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
+
+# 8k working area at base of ram
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
+
+#flash configuration
+flash bank stellaris 0 0 0 0 0