-jtag_device 5 0x1 0x1f 0x1e\r
-jtag_nsrst_delay 200\r
-jtag_ntrst_delay 200\r
-target xscale little reset_init 0 pxa255\r
-reset_config trst_and_srst\r
-run_and_halt_time 0 30\r
-\r
-target_script 0 reset /ram/pxa255.init\r
-\r
-#xscale debug_handler 0 0xFFFF0800 # debug handler base address\r
-\r
-trunc /ram/pxa255.init\r
-append /ram/pxa255.init #configuration file for PXA250 Evaluation Board\r
-append /ram/pxa255.init # -----------------------------------------------------\r
-append /ram/pxa255.init #\r
-append /ram/pxa255.init xscale cp15 15 0x00002001 #Enable CP0 and CP13 access\r
-append /ram/pxa255.init #\r
-append /ram/pxa255.init # setup GPIO\r
-append /ram/pxa255.init #\r
-append /ram/pxa255.init mww 0x40E00018 0x00008000 #CPSR0\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x40E0001C 0x00000002 #GPSR1\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x40E00020 0x00000008 #GPSR2\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x40E0000C 0x00008000 #GPDR0\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x40E00054 0x80000000 #GAFR0_L\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x40E00058 0x00188010 #GAFR0_H\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x40E0005C 0x60908018 #GAFR1_L\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x40E0000C 0x0280E000 #GPDR0\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x40E00010 0x821C88B2 #GPDR1\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x40E00014 0x000F03DB #GPDR2\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x40E00000 0x000F03DB #GPLR0\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init \r
-append /ram/pxa255.init \r
-append /ram/pxa255.init mww 0x40F00004 0x00000020 #PSSR\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init \r
-append /ram/pxa255.init #\r
-append /ram/pxa255.init # setup memory controller\r
-append /ram/pxa255.init #\r
-append /ram/pxa255.init mww 0x48000008 0x01111998 #MSC0\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x48000010 0x00047ff0 #MSC2\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x48000014 0x00000000 #MECR\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x48000028 0x00010504 #MCMEM0\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x4800002C 0x00010504 #MCMEM1\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x48000030 0x00010504 #MCATT0\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x48000034 0x00010504 #MCATT1\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x48000038 0x00004715 #MCIO0\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x4800003C 0x00004715 #MCIO1\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init #\r
-append /ram/pxa255.init mww 0x48000004 0x03CA4018 #MDREF\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x48000004 0x004B4018 #MDREF\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x48000004 0x000B4018 #MDREF\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x48000004 0x000BC018 #MDREF\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x48000000 0x00001AC8 #MDCNFG\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init \r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init \r
-append /ram/pxa255.init mww 0x48000000 0x00001AC9 #MDCNFG\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init mww 0x48000040 0x00000000 #MDMRS\r
-append /ram/pxa255.init sleep 20\r
-append /ram/pxa255.init \r
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME pxa255
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa255
+$_TARGETNAME configure -event reset-init {
+ xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
+ #
+ # setup GPIO
+ #
+ mww 0x40E00018 0x00008000 #CPSR0
+ sleep 20
+ mww 0x40E0001C 0x00000002 #GPSR1
+ sleep 20
+ mww 0x40E00020 0x00000008 #GPSR2
+ sleep 20
+ mww 0x40E0000C 0x00008000 #GPDR0
+ sleep 20
+ mww 0x40E00054 0x80000000 #GAFR0_L
+ sleep 20
+ mww 0x40E00058 0x00188010 #GAFR0_H
+ sleep 20
+ mww 0x40E0005C 0x60908018 #GAFR1_L
+ sleep 20
+ mww 0x40E0000C 0x0280E000 #GPDR0
+ sleep 20
+ mww 0x40E00010 0x821C88B2 #GPDR1
+ sleep 20
+ mww 0x40E00014 0x000F03DB #GPDR2
+ sleep 20
+ mww 0x40E00000 0x000F03DB #GPLR0
+ sleep 20
+
+
+ mww 0x40F00004 0x00000020 #PSSR
+ sleep 20
+
+ #
+ # setup memory controller
+ #
+ mww 0x48000008 0x01111998 #MSC0
+ sleep 20
+ mww 0x48000010 0x00047ff0 #MSC2
+ sleep 20
+ mww 0x48000014 0x00000000 #MECR
+ sleep 20
+ mww 0x48000028 0x00010504 #MCMEM0
+ sleep 20
+ mww 0x4800002C 0x00010504 #MCMEM1
+ sleep 20
+ mww 0x48000030 0x00010504 #MCATT0
+ sleep 20
+ mww 0x48000034 0x00010504 #MCATT1
+ sleep 20
+ mww 0x48000038 0x00004715 #MCIO0
+ sleep 20
+ mww 0x4800003C 0x00004715 #MCIO1
+ sleep 20
+ #
+ mww 0x48000004 0x03CA4018 #MDREF
+ sleep 20
+ mww 0x48000004 0x004B4018 #MDREF
+ sleep 20
+ mww 0x48000004 0x000B4018 #MDREF
+ sleep 20
+ mww 0x48000004 0x000BC018 #MDREF
+ sleep 20
+ mww 0x48000000 0x00001AC8 #MDCNFG
+ sleep 20
+
+ sleep 20
+
+ mww 0x48000000 0x00001AC9 #MDCNFG
+ sleep 20
+ mww 0x48000040 0x00000000 #MDMRS
+ sleep 20
+}
+
+reset_config trst_and_srst
+
+
+
+#xscale debug_handler 0 0xFFFF0800 # debug handler base address
+
projects / openocd / blobdiff