LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
/* move pc from buffer to register cache */
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
- armv4_5->core_cache->reg_list[15].dirty = 1;
- armv4_5->core_cache->reg_list[15].valid = 1;
+ buf_set_u32(armv4_5->pc->value, 0, 32, buffer[1]);
+ armv4_5->pc->dirty = 1;
+ armv4_5->pc->valid = 1;
LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
/* move data from buffer to register cache */
moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
/* stored PC (for calculating fixup) */
- pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ pc = buf_get_u32(armv4_5->pc->value, 0, 32);
switch (moe)
{
}
/* apply PC fixup */
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
+ buf_set_u32(armv4_5->pc->value, 0, 32, pc);
/* on the first debug entry, identify cache type */
if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
+ buf_set_u32(armv4_5->pc->value, 0, 32, address);
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
/* if we're at the reset vector, we have to simulate the branch */
if (current_pc == 0x0)
{
arm_simulate_step(target, NULL);
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
}
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
{
- if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
+ breakpoint = breakpoint_find(target,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
+ if (breakpoint != NULL)
{
uint32_t next_pc;
}
/* send PC */
- xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
- LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ xscale_send_u32(target,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
+ LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
/* wait for and process debug entry */
xscale_debug_entry(target);
}
/* send PC */
- xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
- LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ xscale_send_u32(target, buf_get_u32(armv4_5->pc->value, 0, 32));
+ LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
target->debug_reason = DBG_REASON_NOTHALTED;
if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
{
uint32_t current_opcode, current_pc;
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
target_read_u32(target, current_pc, ¤t_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
}
/* send PC */
- if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK)
+ retval = xscale_send_u32(target,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
+ if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
uint32_t address, int handle_breakpoints)
{
struct arm *armv4_5 = target_to_arm(target);
- struct breakpoint *breakpoint = target->breakpoints;
+ struct breakpoint *breakpoint = NULL;
uint32_t current_pc;
int retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
+ buf_set_u32(armv4_5->pc->value, 0, 32, address);
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
/* if we're at the reset vector, we have to simulate the step */
if (current_pc == 0x0)
{
if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK)
return retval;
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
target->debug_reason = DBG_REASON_SINGLESTEP;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
- if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
- {
- if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK)
- return retval;
- }
+ breakpoint = breakpoint_find(target,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
+ if (breakpoint != NULL) {
+ retval = xscale_unset_breakpoint(target, breakpoint);
+ if (retval != ERROR_OK)
+ return retval;
+ }
retval = xscale_step_inner(target, current, address, handle_breakpoints);
(*trace_data_p)->next = NULL;
(*trace_data_p)->chkpt0 = trace_buffer[256];
(*trace_data_p)->chkpt1 = trace_buffer[257];
- (*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ (*trace_data_p)->last_instruction =
+ buf_get_u32(armv4_5->pc->value, 0, 32);
(*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
(*trace_data_p)->depth = 256 - j;
/* if we enable the trace buffer in fill-once
* mode we know the address of the first instruction */
xscale->trace.pc_ok = 1;
- xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ xscale->trace.current_pc =
+ buf_get_u32(armv4_5->pc->value, 0, 32);
}
else
{
static const struct command_registration xscale_exec_command_handlers[] = {
{
.name = "cache_info",
- .handler = &xscale_handle_cache_info_command,
- .mode = COMMAND_EXEC, NULL,
+ .handler = xscale_handle_cache_info_command,
+ .mode = COMMAND_EXEC,
+ .help = "display information about CPU caches",
},
-
{
.name = "mmu",
- .handler = &xscale_handle_mmu_command,
+ .handler = xscale_handle_mmu_command,
.mode = COMMAND_EXEC,
- .usage = "[enable|disable]",
.help = "enable or disable the MMU",
+ .usage = "['enable'|'disable']",
},
{
.name = "icache",
- .handler = &xscale_handle_idcache_command,
+ .handler = xscale_handle_idcache_command,
.mode = COMMAND_EXEC,
- .usage = "[enable|disable]",
- .help = "enable or disable the ICache",
+ .help = "display ICache state, optionally enabling or "
+ "disabling it",
+ .usage = "['enable'|'disable']",
},
{
.name = "dcache",
- .handler = &xscale_handle_idcache_command,
+ .handler = xscale_handle_idcache_command,
.mode = COMMAND_EXEC,
- .usage = "[enable|disable]",
- .help = "enable or disable the DCache",
+ .help = "display DCache state, optionally enabling or "
+ "disabling it",
+ .usage = "['enable'|'disable']",
},
-
{
.name = "vector_catch",
- .handler = &xscale_handle_vector_catch_command,
+ .handler = xscale_handle_vector_catch_command,
.mode = COMMAND_EXEC,
- .help = "mask of vectors that should be caught",
- .usage = "[<mask>]",
+ .help = "set or display 8-bit mask of vectors "
+ "that should trigger debug entry",
+ .usage = "[mask]",
},
{
.name = "vector_table",
- .handler = &xscale_handle_vector_table_command,
+ .handler = xscale_handle_vector_table_command,
.mode = COMMAND_EXEC,
- .usage = "<high|low> <index> <code>",
- .help = "set static code for exception handler entry",
+ .help = "set vector table entry in mini-ICache, "
+ "or display current tables",
+ .usage = "[('high'|'low') index code]",
},
-
{
.name = "trace_buffer",
- .handler = &xscale_handle_trace_buffer_command,
+ .handler = xscale_handle_trace_buffer_command,
.mode = COMMAND_EXEC,
- .usage = "<enable | disable> [fill [n]|wrap]",
+ .help = "display trace buffer status, enable or disable "
+ "tracing, and optionally reconfigure trace mode",
+ .usage = "['enable'|'disable' ['fill' number|'wrap']]",
},
{
.name = "dump_trace",
- .handler = &xscale_handle_dump_trace_command,
+ .handler = xscale_handle_dump_trace_command,
.mode = COMMAND_EXEC,
- .help = "dump content of trace buffer to <file>",
- .usage = "<file>",
+ .help = "dump content of trace buffer to file",
+ .usage = "filename",
},
{
.name = "analyze_trace",
- .handler = &xscale_handle_analyze_trace_buffer_command,
+ .handler = xscale_handle_analyze_trace_buffer_command,
.mode = COMMAND_EXEC,
.help = "analyze content of trace buffer",
+ .usage = "",
},
{
.name = "trace_image",
- .handler = &xscale_handle_trace_image_command,
- COMMAND_EXEC,
- .help = "load image from <file> [base address]",
- .usage = "<file> [address] [type]",
+ .handler = xscale_handle_trace_image_command,
+ .mode = COMMAND_EXEC,
+ .help = "load image from file to address (default 0)",
+ .usage = "filename [offset [filetype]]",
},
-
{
.name = "cp15",
- .handler = &xscale_handle_cp15,
+ .handler = xscale_handle_cp15,
.mode = COMMAND_EXEC,
- .help = "access coproc 15",
- .usage = "<register> [value]",
+ .help = "Read or write coprocessor 15 register.",
+ .usage = "register [value]",
},
COMMAND_REGISTRATION_DONE
};
static const struct command_registration xscale_any_command_handlers[] = {
{
.name = "debug_handler",
- .handler = &xscale_handle_debug_handler_command,
+ .handler = xscale_handle_debug_handler_command,
.mode = COMMAND_ANY,
- .usage = "<target#> <address>",
+ .help = "Change address used for debug handler.",
+ .usage = "target address",
},
{
.name = "cache_clean_address",
- .handler = &xscale_handle_cache_clean_address_command,
+ .handler = xscale_handle_cache_clean_address_command,
.mode = COMMAND_ANY,
+ .help = "Change address used for cleaning data cache.",
+ .usage = "address",
},
{
.chain = xscale_exec_command_handlers,
projects / openocd / blobdiff