uint8_t scratch[4];
memset(&field, 0, sizeof field);
- field.tap = tap;
field.num_bits = tap->ir_length;
field.out_value = scratch;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
- jtag_add_ir_scan(1, &field, jtag_get_end_state());
+ jtag_add_ir_scan(tap, &field, jtag_get_end_state());
}
return ERROR_OK;
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
- fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
- fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
fields[2].in_value = &tmp2;
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 3, fields, jtag_get_end_state());
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
jtag_set_end_state(TAP_IDLE);
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 3, fields, jtag_get_end_state());
/* DANGER!!! this must be here. It will make sure that the arguments
* to jtag_set_check_value() does not go out of scope! */
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].check_value = &field0_check_value;
fields[0].check_mask = &field0_check_mask;
- fields[1].tap = target->tap;
fields[1].num_bits = 32;
- fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].check_value = &field2_check_value;
fields[2].check_mask = &field2_check_mask;
fields[1].in_value = (uint8_t *)(field1 + i);
- jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE));
+ jtag_add_dr_scan_check(target->tap, 3, fields, jtag_set_end_state(TAP_IDLE));
jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].in_value = &field0_in;
- fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
- fields[2].tap = target->tap;
fields[2].num_bits = 1;
uint8_t tmp;
fields[2].in_value = &tmp;
jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
}
- jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
+ jtag_add_dr_scan(target->tap, 3, fields, jtag_set_end_state(TAP_IDLE));
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0_out;
fields[0].in_value = &field0_in;
- fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
- fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp;
LOG_DEBUG("polling RX");
for (;;)
{
- jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
+ jtag_add_dr_scan(target->tap, 3, fields, jtag_set_end_state(TAP_IDLE));
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
/* set rx_valid */
field2 = 0x1;
- jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
+ jtag_add_dr_scan(target->tap, 3, fields, jtag_set_end_state(TAP_IDLE));
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
- fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
- fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
fields[2].in_value = &tmp2;
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 3, fields, jtag_get_end_state());
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
- fields[1].tap = target->tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
- jtag_add_dr_scan(2, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 2, fields, jtag_get_end_state());
/* rest of packet is a cacheline: 8 instructions, with parity */
fields[0].num_bits = 32;
memcpy(&value, packet, sizeof(uint32_t));
cmd = parity(value);
- jtag_add_dr_scan(2, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 2, fields, jtag_get_end_state());
}
return jtag_execute_queue();
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
- fields[1].tap = target->tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
- jtag_add_dr_scan(2, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 2, fields, jtag_get_end_state());
return ERROR_OK;
}
LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
/* move pc from buffer to register cache */
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
- armv4_5->core_cache->reg_list[15].dirty = 1;
- armv4_5->core_cache->reg_list[15].valid = 1;
+ buf_set_u32(armv4_5->pc->value, 0, 32, buffer[1]);
+ armv4_5->pc->dirty = 1;
+ armv4_5->pc->valid = 1;
LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
/* move data from buffer to register cache */
moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
/* stored PC (for calculating fixup) */
- pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ pc = buf_get_u32(armv4_5->pc->value, 0, 32);
switch (moe)
{
}
/* apply PC fixup */
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
+ buf_set_u32(armv4_5->pc->value, 0, 32, pc);
/* on the first debug entry, identify cache type */
if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
+ buf_set_u32(armv4_5->pc->value, 0, 32, address);
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
/* if we're at the reset vector, we have to simulate the branch */
if (current_pc == 0x0)
{
arm_simulate_step(target, NULL);
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
}
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
{
- if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
+ breakpoint = breakpoint_find(target,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
+ if (breakpoint != NULL)
{
uint32_t next_pc;
}
/* send PC */
- xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
- LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ xscale_send_u32(target,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
+ LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
/* wait for and process debug entry */
xscale_debug_entry(target);
}
/* send PC */
- xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
- LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ xscale_send_u32(target, buf_get_u32(armv4_5->pc->value, 0, 32));
+ LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
target->debug_reason = DBG_REASON_NOTHALTED;
if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
{
uint32_t current_opcode, current_pc;
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
target_read_u32(target, current_pc, ¤t_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
}
/* send PC */
- if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK)
+ retval = xscale_send_u32(target,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
+ if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
uint32_t address, int handle_breakpoints)
{
struct arm *armv4_5 = target_to_arm(target);
- struct breakpoint *breakpoint = target->breakpoints;
+ struct breakpoint *breakpoint = NULL;
uint32_t current_pc;
int retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
+ buf_set_u32(armv4_5->pc->value, 0, 32, address);
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
/* if we're at the reset vector, we have to simulate the step */
if (current_pc == 0x0)
{
if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK)
return retval;
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
target->debug_reason = DBG_REASON_SINGLESTEP;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
- if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
- {
- if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK)
- return retval;
- }
+ breakpoint = breakpoint_find(target,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
+ if (breakpoint != NULL) {
+ retval = xscale_unset_breakpoint(target, breakpoint);
+ if (retval != ERROR_OK)
+ return retval;
+ }
retval = xscale_step_inner(target, current, address, handle_breakpoints);
(*trace_data_p)->next = NULL;
(*trace_data_p)->chkpt0 = trace_buffer[256];
(*trace_data_p)->chkpt1 = trace_buffer[257];
- (*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ (*trace_data_p)->last_instruction =
+ buf_get_u32(armv4_5->pc->value, 0, 32);
(*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
(*trace_data_p)->depth = 256 - j;
return ERROR_OK;
}
- bool icache;
- COMMAND_PARSE_BOOL(CMD_NAME, icache, "icache", "dcache");
-
+ bool icache = false;
+ if (strcmp(CMD_NAME, "icache") == 0)
+ icache = true;
if (CMD_ARGC >= 1)
{
bool enable;
/* if we enable the trace buffer in fill-once
* mode we know the address of the first instruction */
xscale->trace.pc_ok = 1;
- xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ xscale->trace.current_pc =
+ buf_get_u32(armv4_5->pc->value, 0, 32);
}
else
{