int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
+int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
.read_memory = xscale_read_memory,
.write_memory = xscale_write_memory,
.bulk_write_memory = xscale_bulk_write_memory,
-
+ .checksum_memory = xscale_checksum_memory,
+
.run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = xscale_add_breakpoint,
return ERROR_OK;
}
+int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
+{
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+}
+
u32 xscale_get_ttb(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale->trace.buffer_fill = -1;
}
+ if (xscale->trace.buffer_enabled)
+ {
+ /* if we enable the trace buffer in fill-once
+ * mode we know the address of the first instruction */
+ xscale->trace.pc_ok = 1;
+ xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ }
+ else
+ {
+ /* otherwise the address is unknown, and we have no known good PC */
+ xscale->trace.pc_ok = 0;
+ }
+
command_print(cmd_ctx, "trace buffer %s (%s)",
(xscale->trace.buffer_enabled) ? "enabled" : "disabled",
(xscale->trace.buffer_fill > 0) ? "fill" : "wrap");