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arm7_9_common: use register_commands()
[openocd] / src / target / xscale.c
diff --git a/src/target/xscale.c b/src/target/xscale.c
index c908fd709502e1d4dd467886e266cfd3344d293c..c2b34931de57299751d02479e2c7cae1ff4fd392 100644 (file)
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -833,7 +833,7 @@ static int xscale_update_vectors(struct target *target)
 static int xscale_arch_state(struct target *target)
 {
        struct xscale_common *xscale = target_to_xscale(target);
-       struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+       struct arm *armv4_5 = &xscale->armv4_5_common;
 
        static const char *state[] =
        {
@@ -858,7 +858,7 @@ static int xscale_arch_state(struct target *target)
                         armv4_5_state_strings[armv4_5->core_state],
                         Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
                         arm_mode_name(armv4_5->core_mode),
-                        buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
+                        buf_get_u32(armv4_5->cpsr->value, 0, 32),
                         buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
                         state[xscale->armv4_5_mmu.mmu_enabled],
                         state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
@@ -911,7 +911,7 @@ static int xscale_poll(struct target *target)
 static int xscale_debug_entry(struct target *target)
 {
        struct xscale_common *xscale = target_to_xscale(target);
-       struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+       struct arm *armv4_5 = &xscale->armv4_5_common;
        uint32_t pc;
        uint32_t buffer[10];
        int i;
@@ -948,12 +948,9 @@ static int xscale_debug_entry(struct target *target)
                LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
        }
 
-       buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
-       armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
-       armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+       arm_set_cpsr(armv4_5, buffer[9]);
        LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
 
-       armv4_5->core_mode = buffer[9] & 0x1f;
        if (!is_arm_mode(armv4_5->core_mode))
        {
                target->state = TARGET_UNKNOWN;
@@ -963,12 +960,6 @@ static int xscale_debug_entry(struct target *target)
        LOG_DEBUG("target entered debug state in %s mode",
                         arm_mode_name(armv4_5->core_mode));
 
-       if (buffer[9] & 0x20)
-               armv4_5->core_state = ARMV4_5_STATE_THUMB;
-       else
-               armv4_5->core_state = ARMV4_5_STATE_ARM;
-
-
        /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
        if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
        {
@@ -1188,7 +1179,7 @@ static int xscale_resume(struct target *target, int current,
                uint32_t address, int handle_breakpoints, int debug_execution)
 {
        struct xscale_common *xscale = target_to_xscale(target);
-       struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+       struct arm *armv4_5 = &xscale->armv4_5_common;
        struct breakpoint *breakpoint = target->breakpoints;
        uint32_t current_pc;
        int retval;
@@ -1260,8 +1251,10 @@ static int xscale_resume(struct target *target, int current,
                                xscale_send_u32(target, 0x30);
 
                        /* send CPSR */
-                       xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
-                       LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+                       xscale_send_u32(target,
+                               buf_get_u32(armv4_5->cpsr->value, 0, 32));
+                       LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+                               buf_get_u32(armv4_5->cpsr->value, 0, 32));
 
                        for (i = 7; i >= 0; i--)
                        {
@@ -1303,8 +1296,9 @@ static int xscale_resume(struct target *target, int current,
                xscale_send_u32(target, 0x30);
 
        /* send CPSR */
-       xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
-       LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+       xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32));
+       LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+                       buf_get_u32(armv4_5->cpsr->value, 0, 32));
 
        for (i = 7; i >= 0; i--)
        {
@@ -1341,7 +1335,7 @@ static int xscale_step_inner(struct target *target, int current,
                uint32_t address, int handle_breakpoints)
 {
        struct xscale_common *xscale = target_to_xscale(target);
-       struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+       struct arm *armv4_5 = &xscale->armv4_5_common;
        uint32_t next_pc;
        int retval;
        int i;
@@ -1381,9 +1375,12 @@ static int xscale_step_inner(struct target *target, int current,
                        return retval;
 
        /* send CPSR */
-       if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
+       retval = xscale_send_u32(target,
+                       buf_get_u32(armv4_5->cpsr->value, 0, 32));
+       if (retval != ERROR_OK)
                return retval;
-       LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+       LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+                       buf_get_u32(armv4_5->cpsr->value, 0, 32));
 
        for (i = 7; i >= 0; i--)
        {
@@ -1419,7 +1416,7 @@ static int xscale_step_inner(struct target *target, int current,
 static int xscale_step(struct target *target, int current,
                uint32_t address, int handle_breakpoints)
 {
-       struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_armv4_5(target);
        struct breakpoint *breakpoint = target->breakpoints;
 
        uint32_t current_pc;
@@ -1664,7 +1661,7 @@ static int xscale_write_core_reg(struct target *target, struct reg *r,
 
 static int xscale_full_context(struct target *target)
 {
-       struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_armv4_5(target);
 
        uint32_t *buffer;
 
@@ -1740,7 +1737,7 @@ static int xscale_full_context(struct target *target)
 
 static int xscale_restore_context(struct target *target)
 {
-       struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_armv4_5(target);
 
        int i, j;
 
@@ -2473,7 +2470,7 @@ static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
 static int xscale_read_trace(struct target *target)
 {
        struct xscale_common *xscale = target_to_xscale(target);
-       struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+       struct arm *armv4_5 = &xscale->armv4_5_common;
        struct xscale_trace_data **trace_data_p;
 
        /* 258 words from debug handler
@@ -2824,7 +2821,7 @@ static const struct reg_arch_type xscale_reg_type = {
 static void xscale_build_reg_cache(struct target *target)
 {
        struct xscale_common *xscale = target_to_xscale(target);
-       struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+       struct arm *armv4_5 = &xscale->armv4_5_common;
        struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
        struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
        int i;
@@ -3274,7 +3271,7 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command)
 {
        struct target *target = get_current_target(CMD_CTX);
        struct xscale_common *xscale = target_to_xscale(target);
-       struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+       struct arm *armv4_5 = &xscale->armv4_5_common;
        uint32_t dcsr_value;
        int retval;
 
@@ -3561,27 +3558,27 @@ static int xscale_register_commands(struct command_context *cmd_ctx)
 {
        struct command *xscale_cmd;
 
-       xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
+       xscale_cmd = COMMAND_REGISTER(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
 
-       register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler <target#> <address>' command takes two required operands");
-       register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler <target#> <address>' command takes two required operands");
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
 
-       register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
-       register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
-       register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
-       register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
 
-       register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
-       register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, "<high|low> <index> <code> set static code for exception handler entry");
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, "<high|low> <index> <code> set static code for exception handler entry");
 
-       register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable | disable> ['fill' [n]|'wrap']");
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable | disable> ['fill' [n]|'wrap']");
 
-       register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
-       register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
-       register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command,
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command,
                COMMAND_EXEC, "load image from <file> [base address]");
 
-       register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
+       COMMAND_REGISTER(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
 
        armv4_5_register_commands(cmd_ctx);
 
Cloned from https://git.code.sf.net/p/openocd/code