#ifndef XSCALE_H
#define XSCALE_H
-#include "armv4_5.h"
+#include "arm.h"
#include "armv4_5_mmu.h"
#include "trace.h"
#define XSCALE_LDIC 0x07
#define XSCALE_SELDCSR 0x09
+/* Possible CPU types */
+#define XSCALE_IXP4XX_PXA2XX 0x0
+#define XSCALE_PXA3XX 0x4
+
enum xscale_debug_reason
{
XSCALE_DBG_REASON_GENERIC,
int buffer_fill; /* maximum number of trace runs to read (-1 for wrap-around) */
int pc_ok;
uint32_t current_pc;
- armv4_5_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
+ enum arm_state core_state; /* current core state (ARM, Thumb) */
};
struct xscale_common
uint32_t cp15_control_reg;
int fast_memory_access;
+
+ /* CPU variant */
+ int xscale_variant;
};
static inline struct xscale_common *