make OMAP5912 resets more reliable

[openocd] / tcl / target / davinci.cfg

diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index 0a3da27d50aa4a33e19bcf988abed39e0d1ad565..658e7fe5bc2f5cea1d31c5e8bce63cf547a662f1 100644 (file)
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -31,12 +31,10 @@ proc mmw {reg setbits clearbits} {
 # For PLLs that don't have a given register (e.g. plldiv8), or where a
 # given divider is non-programmable, caller provides *NO* config mapping.
 #
-# REVISIT there are minor differences between the PLL controllers.
-# Handle those; maybe check the ID register.  This version behaves
-# for at least the dm355.  On dm6446 and dm357 the PLLRST polarity
-# is different.  On dm365 there are more changes.
-#
-proc pll_setup {pll_addr mult config} {
+
+# PLL version 0x02: tested on dm355
+# REVISIT:  On dm6446 and dm357 the PLLRST polarity is different.
+proc pll_v02_setup {pll_addr mult config} {
        set pll_ctrl_addr [expr $pll_addr + 0x100]
        set pll_ctrl [mrw $pll_ctrl_addr]
 
@@ -98,7 +96,7 @@ proc pll_setup {pll_addr mult config} {
                set go 1
        }
        if { [dict exists $config div2] } {
-               1et div [dict get $config div2]
+               set div [dict get $config div2]
                set div [expr 0x8000 | ($div - 1)]
                mww [expr $pll_addr + 0x011c] $div
                set go 1
@@ -106,7 +104,7 @@ proc pll_setup {pll_addr mult config} {
        if { [dict exists $config div3] } {
                set div [dict get $config div3]
                set div [expr 0x8000 | ($div - 1)]
-               mww [expr $pll_addr + 0x011c] $div
+               mww [expr $pll_addr + 0x0120] $div
                set go 1
        }
        if { [dict exists $config div4] } {
@@ -127,6 +125,7 @@ proc pll_setup {pll_addr mult config} {
                set pllstat [expr $pll_addr + 0x013c]
                while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
        }
+       mww [expr $pll_addr + 0x0138] 0x00
 
        # 11 - wait at least 5 usec for reset to finish
        # (assume covered by overheads including JTAG messaging)
@@ -154,7 +153,14 @@ proc psc_enable {module} {
        mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
 }
 
-# execute non-DSP PSC transition(s) set up by psc_enable
+# prepare a non-DSP module to be reset; finish with psc_go
+proc psc_reset {module} {
+       set psc_addr 0x01c41000
+       # write MDCTL
+       mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
+}
+
+# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
 proc psc_go {} {
        set psc_addr 0x01c41000
        set ptstat_addr [expr $psc_addr + 0x0128]