target.cfg: label ETBs correctly

[openocd] / tcl / target / str912.cfg

diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg
index 705326b5e775a0e5d7aef4437525a0353cfa3f6d..0dd684835d3358a2e7c9b62c377e39a21bf52a68 100644 (file)
--- a/tcl/target/str912.cfg
+++ b/tcl/target/str912.cfg
@@ -1,14 +1,14 @@
 # script for str9
 
-if { [info exists CHIPNAME] } {        
-   set  _CHIPNAME $CHIPNAME    
-} else {        
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME str912
 }
 
-if { [info exists ENDIAN] } {  
-   set  _ENDIAN $ENDIAN    
-} else {        
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
@@ -43,7 +43,7 @@ if { [info exists BSTAPID ] } {
 }
 jtag newtap $_CHIPNAME bs    -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
 
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
 
 $_TARGETNAME configure -event reset-start { jtag_rclk 16 }
@@ -51,16 +51,16 @@ $_TARGETNAME configure -event reset-start { jtag_rclk 16 }
 $_TARGETNAME configure -event reset-init {
        # We can increase speed now that we know the target is halted.
        #jtag_rclk 3000
-       
+
        # -- Enable 96K RAM
        # PFQBC enabled / DTCM & AHB wait-states disabled
-       mww 0x5C002034 0x0191 
+       mww 0x5C002034 0x0191
 
        str9x flash_config 0 4 2 0 0x80000
        flash protect 0 0 7 off
 }
 
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
 
 #flash bank str9x <base> <size> 0 0 <target#> <variant>
 flash bank str9x 0x00000000 0x00080000 0 0 0