#ifndef _IMXIMAGE_H_
#define _IMXIMAGE_H_
-#include <config.h>
-
#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
#define APP_CODE_BARKER 0xB1
#define HEADER_OFFSET 0x400
+/*
+ * NOTE: This file must be kept in sync with arch/arm/include/asm/\
+ * imx-common/imximage.cfg because tools/imximage.c can not
+ * cross-include headers from arch/arm/ and vice-versa.
+ */
#define CMD_DATA_STR "DATA"
+#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
#define FLASH_OFFSET_STANDARD 0x400
#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_ONENAND 0x100
+#define FLASH_OFFSET_NOR 0x1000
+#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
#define IVT_HEADER_TAG 0xD1
#define IVT_VERSION 0x40
CMD_INVALID,
CMD_IMAGE_VERSION,
CMD_BOOT_FROM,
+ CMD_BOOT_OFFSET,
CMD_DATA
};
dcd_v2_t dcd_table;
} imx_header_v2_t;
+/* The header must be aligned to 4k on MX53 for NAND boot */
struct imx_header {
union {
imx_header_v1_t hdr_v1;
imx_header_v2_t hdr_v2;
} header;
uint32_t flash_offset;
-};
+} __attribute__((aligned(4096)));
typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
char *name, int lineno,
uint32_t dcd_len,
char *name, int lineno);
-typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr,
- uint32_t dcd_len,
- struct stat *sbuf,
- struct mkimage_params *params);
+typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+ uint32_t entry_point, uint32_t flash_offset);
#endif /* _IMXIMAGE_H_ */