git.sur5r.net Git - freertos/commit

]> git.sur5r.net Git - freertos/commit

author	rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
	Tue, 7 Mar 2017 04:06:10 +0000 (04:06 +0000)
committer	rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
	Tue, 7 Mar 2017 04:06:10 +0000 (04:06 +0000)
commit	13421c579a500c8430593a20cef384ba2a092f9d
tree	4ff4724fd24b419e1470e697e1c7e33c44369d46	tree \| snapshot
parent	536ea7c7ffbb091d458c71bef7defc17016db840	commit \| diff

Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across asm code as optimisers get more aggressive.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2487 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

16 files changed:

FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CA9/port.c		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CM0/port.c		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CM3/port.c		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CR5/port.c		diff \| blob \| history
FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h		diff \| blob \| history

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