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armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency
authorMingkai Hu <mingkai.hu@nxp.com>
Wed, 7 Sep 2016 09:56:08 +0000 (17:56 +0800)
committerYork Sun <york.sun@nxp.com>
Wed, 14 Sep 2016 21:10:02 +0000 (14:10 -0700)
commit13f7988067856845ef593795003160db5ccf43cd
treea5bc36d5777e7938a0c7198fd9e94b3d9174f70etree | snapshot
parent9578c4273d4b9d24403bf4e03d7729f381527cd8commit | diff
armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency

According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S diff | blob | history
Cloned from git://git.denx.de/u-boot.git