]> git.sur5r.net Git - u-boot/commit
mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600
authorStefan Roese <sr@denx.de>
Wed, 2 Sep 2015 12:29:12 +0000 (14:29 +0200)
committerTom Rini <trini@konsulko.com>
Fri, 11 Sep 2015 21:15:13 +0000 (17:15 -0400)
commit1a103c6caa0b27fcd3798267b980444f5459860f
tree5cf3d03804ff4d29d1968fefbbcf6ea8a53222b8
parentb9599dd857b3f6ed9c7c7e7438dffb84ee5ce1a0
mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600

This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC strength.
The SPEAr600 HW ECC only supports 1-bit ECC strength.

To enable SW BCH4, you need to specify this in your config header:

#define CONFIG_NAND_ECC_BCH
#define CONFIG_BCH

And use the command "nandecc bch4" to select this ECC scheme upon runtime.

Tested on SPEAr600 x600 board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
drivers/mtd/nand/fsmc_nand.c