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arm: socfpga: Fix ArriaV SoCDK PLL config
authorMarek Vasut <marex@denx.de>
Wed, 19 Aug 2015 05:46:49 +0000 (07:46 +0200)
committerMarek Vasut <marex@denx.de>
Sun, 23 Aug 2015 09:56:21 +0000 (11:56 +0200)
commit29aa439759ed2e5dfa45cd8d6d5a1d51604e3820
treebfda5c57dc97c8c8f49849e572ef649ebaa2b1f5tree | snapshot
parent9238b52abd788cf4c2311896a5ada34ecff5499ccommit | diff
arm: socfpga: Fix ArriaV SoCDK PLL config

Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.

Signed-off-by: Marek Vasut <marex@denx.de>
board/altera/arria5-socdk/qts/pll_config.h diff | blob | history
Cloned from git://git.denx.de/u-boot.git