]> git.sur5r.net Git - u-boot/commit
arm: rmobile: r8a7790: Update initialize L2 cache
authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Fri, 31 Oct 2014 07:07:16 +0000 (16:07 +0900)
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Mon, 3 Nov 2014 23:57:58 +0000 (08:57 +0900)
commit3372a9a7a83ca62f5d3536afef8aec6ac553ad9e
treef8294873703a494b984dffe26b297565ee889350
parent571bdf16a78e9e116a93d46f4809c4f8a3f2adb6
arm: rmobile: r8a7790: Update initialize L2 cache

Initialization of L2CTLR[5] was set only as R8A7790 by commit
237faf095fb43abbed6e40266ef7efccc8b9308b.
However, initialization of cash needs to be performed continuously.
This changes into the processing which continues initialization of
L2CTLR[5] into L2CTLR cash and performs it.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S