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(parent: d1001e3) | patch
powerpc/corenet2: fix mismatch DDR sync bit from RCW
authorYork Sun <yorksun@freescale.com>
Mon, 8 Oct 2012 07:44:16 +0000 (07:44 +0000)
committerAndy Fleming <afleming@freescale.com>
Mon, 22 Oct 2012 19:31:20 +0000 (14:31 -0500)
commit379c5145ef8f3adbcfeb0a47503838627959cb67
treed3125ad2d838363ae8b4eb617a38620f19c6e12ctree | snapshot
parentd1001e3f0ce0059a55a870c42bac8aba2e4befeccommit | diff
powerpc/corenet2: fix mismatch DDR sync bit from RCW

Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
arch/powerpc/cpu/mpc85xx/cpu.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git