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(parent: 148ba55) | patch
zynq: slcr: Wait 100ms till clk is properly setup
authorMichal Simek <michal.simek@xilinx.com>
Wed, 8 May 2013 13:37:28 +0000 (15:37 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 12 Aug 2013 06:59:55 +0000 (08:59 +0200)
commit39523bef29f71967247ca00fe4b2c7e0831bb8a2
tree13eb99a9c67cb1a21cadfb5089249310be548abdtree | snapshot
parent148ba55cc618eaca19d7c86bdc003a7a71ee3a92commit | diff
zynq: slcr: Wait 100ms till clk is properly setup

If you don't wait you will loose the first sent packet
even all bits in emacps are correctly setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
arch/arm/cpu/armv7/zynq/slcr.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git