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(parent: de51916) | patch
driver/ddr: Fix DDR register timing_cfg_8
authorYork Sun <yorksun@freescale.com>
Thu, 26 Jun 2014 18:14:44 +0000 (11:14 -0700)
committerYork Sun <yorksun@freescale.com>
Tue, 22 Jul 2014 23:25:55 +0000 (16:25 -0700)
commit3d75ec95f57224995210db5c5dea8d458cf862fb
tree4ad21c2e982302743b1d220ae669eef3a26fbb18tree | snapshot
parentde5191631088e71ba8ed28bb491dafa776058008commit | diff
driver/ddr: Fix DDR register timing_cfg_8

The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun <yorksun@freescale.com>
drivers/ddr/fsl/ctrl_regs.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git